30 lines
703 B
Python
30 lines
703 B
Python
from migen import *
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# Our simple counter, which increments at every cycle.
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class Counter(Module):
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def __init__(self):
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self.count = Signal(4)
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# At each cycle, increase the value of the count signal.
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# We do it with convertible/synthesizable FHDL code.
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self.sync += self.count.eq(self.count + 1)
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# Simply read the count signal and print it.
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# The output is:
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# Count: 0
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# Count: 1
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# Count: 2
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# ...
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def counter_test(dut):
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for i in range(20):
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print((yield dut.count)) # read and print
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yield # next clock cycle
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# simulation ends with this generator
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if __name__ == "__main__":
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dut = Counter()
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Simulator(dut, counter_test(dut)).run()
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