Florent Kermarrec ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" ... This probably breaks simulation with Icarus Verilog (and others simulators?)		2015-03-18 14:59:22 +01:00
..
altera	mibuild/altera: use new Toolchain/Platform architecture	2015-03-16 21:07:55 +01:00
lattice	mibuild/lattice: use ODDRXD1 and new synthesis directive	2015-03-17 14:59:36 +01:00
platforms	mibuild/platform/versa: fix clock_constraints	2015-03-17 15:25:10 +01:00
sim	mibuild/sim: clean up (thanks sb)	2015-03-10 16:41:52 +01:00
xilinx	mibuild/xilinx/common: add XilinxDDROutput	2015-03-16 22:53:05 +01:00
__init__.py
generic_platform.py	fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"	2015-03-18 14:59:22 +01:00
generic_programmer.py
tools.py