113 lines
3.5 KiB
Python
113 lines
3.5 KiB
Python
from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.xilinx.common import CRG_DS
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from mibuild.xilinx.ise import XilinxISEPlatform
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from mibuild.xilinx.vivado import XilinxVivadoPlatform
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from mibuild.xilinx.programmer import *
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_io = [
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("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
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("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
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("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
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("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
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("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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("clk156", 0,
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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),
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("serial", 0,
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Subsignal("cts", Pins("L27")),
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Subsignal("rts", Pins("K23")),
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Subsignal("tx", Pins("K24")),
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Subsignal("rx", Pins("M19")),
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IOStandard("LVCMOS25")
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("M28")),
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Subsignal("gtx", Pins("K30")),
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Subsignal("rx", Pins("U27")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("L20")),
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Subsignal("int_n", Pins("N30")),
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Subsignal("mdio", Pins("J21")),
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Subsignal("mdc", Pins("R23")),
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Subsignal("dv", Pins("R28")),
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Subsignal("rx_er", Pins("V26")),
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Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")),
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Subsignal("tx_en", Pins("M27")),
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Subsignal("tx_er", Pins("N29")),
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Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")),
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Subsignal("col", Pins("W19")),
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Subsignal("crs", Pins("R30")),
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IOStandard("LVCMOS25")
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),
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]
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def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
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if toolchain == "ise":
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xilinx_platform = XilinxISEPlatform
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elif toolchain == "vivado":
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xilinx_platform = XilinxVivadoPlatform
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else:
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raise ValueError
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class RealPlatform(xilinx_platform):
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bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
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def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset")):
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xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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def create_programmer(self):
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if programmer == "xc3sprog":
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return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
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elif programmer == "vivado":
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return VivadoProgrammer()
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else:
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raise ValueError
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
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except ConstraintError:
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pass
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self.add_platform_command("""
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create_clock -name sys_clk -period 6 [get_nets sys_clk]
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create_clock -name eth_rx_clk -period 8 [get_nets eth_rx_clk]
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create_clock -name eth_tx_clk -period 8 [get_nets eth_tx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
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set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
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set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 2.5 [current_design]
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""")
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return RealPlatform(*args, **kwargs)
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