139 lines
5.9 KiB
Python
139 lines
5.9 KiB
Python
# This file is Copyright (c) 2014 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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import subprocess
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import sys
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from migen.fhdl.structure import _Fragment
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from migen.build.generic_platform import *
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from migen.build import tools
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from migen.build.xilinx import common
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def _format_constraint(c):
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if isinstance(c, Pins):
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return "set_property LOC " + c.identifiers[0]
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elif isinstance(c, IOStandard):
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return "set_property IOSTANDARD " + c.name
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elif isinstance(c, Drive):
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return "set_property DRIVE " + str(c.strength)
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elif isinstance(c, Misc):
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return "set_property " + c.misc.replace("=", " ")
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else:
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raise ValueError("unknown constraint {}".format(c))
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def _format_xdc(signame, resname, *constraints):
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fmt_c = [_format_constraint(c) for c in constraints]
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fmt_r = resname[0] + ":" + str(resname[1])
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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r = " ## {}\n".format(fmt_r)
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for c in fmt_c:
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r += c + " [get_ports " + signame + "]\n"
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return r
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def _build_xdc(named_sc, named_pc):
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r = ""
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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r += _format_xdc(sig + "[" + str(i) + "]", resname, Pins(p), *others)
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elif pins:
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r += _format_xdc(sig, resname, Pins(pins[0]), *others)
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else:
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r += _format_xdc(sig, resname, *others)
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if named_pc:
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r += "\n" + "\n\n".join(named_pc)
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return r
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def _run_vivado(build_name, vivado_path, source, ver=None):
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if sys.platform == "win32" or sys.platform == "cygwin":
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build_script_contents = "REM Autogenerated by Migen\n"
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build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
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build_script_file = "build_" + build_name + ".bat"
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tools.write_to_file(build_script_file, build_script_contents)
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r = subprocess.call([build_script_file])
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else:
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build_script_contents = "# Autogenerated by Migen\nset -e\n"
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settings = common.settings(vivado_path, ver)
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build_script_contents += "source " + settings + "\n"
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build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
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build_script_file = "build_" + build_name + ".sh"
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tools.write_to_file(build_script_file, build_script_contents)
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r = subprocess.call(["bash", build_script_file])
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if r != 0:
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raise OSError("Subprocess failed")
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class XilinxVivadoToolchain:
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def __init__(self):
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self.bitstream_commands = []
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self.additional_commands = []
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self.pre_synthesis_commands = []
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self.with_phys_opt = False
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def _build_batch(self, platform, sources, build_name):
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tcl = []
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for filename, language, library in sources:
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filename_tcl = "{" + filename + "}"
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tcl.append("add_files " + filename_tcl)
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tcl.append("set_property library {} [get_files {}]"
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.format(library, filename_tcl))
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tcl.append("read_xdc {}.xdc".format(build_name))
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tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
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tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths)))
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
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tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
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tcl.append("place_design")
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if self.with_phys_opt:
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tcl.append("phys_opt_design -directive AddRetime")
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name))
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tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name))
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tcl.append("report_io -file {}_io.rpt".format(build_name))
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tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
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tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
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tcl.append("route_design")
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tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
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tcl.append("report_drc -file {}_drc.rpt".format(build_name))
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tcl.append("report_timing_summary -max_paths 10 -file {}_timing.rpt".format(build_name))
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tcl.append("report_power -file {}_power.rpt".format(build_name))
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for bitstream_command in self.bitstream_commands:
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tcl.append(bitstream_command.format(build_name=build_name))
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tcl.append("write_bitstream -force {}.bit ".format(build_name))
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for additional_command in self.additional_commands:
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tcl.append(additional_command.format(build_name=build_name))
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tcl.append("quit")
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tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
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def build(self, platform, fragment, build_dir="build", build_name="top",
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vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
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tools.mkdir_noerror(build_dir)
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os.chdir(build_dir)
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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v_output = platform.get_verilog(fragment)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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sources = platform.sources | {(v_file, "verilog", "work")}
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self._build_batch(platform, sources, build_name)
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tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
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if run:
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_run_vivado(build_name, vivado_path, source)
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os.chdir("..")
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return v_output.ns
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def add_period_constraint(self, platform, clk, period):
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platform.add_platform_command("""create_clock -name {clk} -period """ + \
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str(period) + """ [get_ports {clk}]""", clk=clk)
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