William D. Jones 5c83c88128 Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run.		2018-09-17 21:17:24 -04:00
..
boards	targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen	2018-09-07 10:37:15 +02:00
build	Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run.	2018-09-17 21:17:24 -04:00
gen	build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)	2018-05-01 12:02:54 +02:00
soc	Merge pull request #99 from cr1901/mk-copy-main-ram	2018-09-08 03:55:23 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00