Sebastien Bourdeauducq bac62a32a9 Make memory ports part of specials ... This is needed to handle cases where a single memory has ports in two different modules, and one of these modules is subject to clock domain remapping. The clock domain of the port in that module only must be remapped.		2013-05-28 16:11:34 +02:00
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__init__.py	pytholite: transformable elements	2012-10-29 18:13:03 +01:00
compiler.py	Make memory ports part of specials	2013-05-28 16:11:34 +02:00
expr.py	Remove Constant	2012-11-28 23:18:43 +01:00
fsm.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00
io.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
reg.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
transel.py	pytholite: support signed registers	2012-11-30 17:07:12 +01:00