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litex/verilog
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Sebastien Bourdeauducq 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete)
2011-12-18 00:29:37 +01:00
..
lm32 Initial import 2011-12-13 17:33:12 +01:00
m1reset Proper reset generation 2011-12-16 22:25:26 +01:00