Karol Gugala 5d0c5d7088 CPU: Vex: add debug slave for dbg cpu variant ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>		2021-01-15 09:28:03 +01:00
..
build	Quartus: handle vh and svh files	2020-12-20 11:53:08 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	CPU: Vex: add debug slave for dbg cpu variant	2021-01-15 09:28:03 +01:00
tools	tools/litex_term: review/simplify a bit PR #772.	2021-01-13 19:33:29 +01:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00