95 lines
2.2 KiB
Python
95 lines
2.2 KiB
Python
#
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# 1:1 frequency-ratio Generic SDR PHY
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#
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# The GENSDRPHY is validated on CycloneIV (Altera) but since it does
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# not use vendor-dependent code, it can also be used on other architectures.
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#
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# The PHY needs 2 Clock domains:
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# - sys_clk : The System Clock domain
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# - sys_clk_ps : The System Clock domain with its phase shifted
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# (-3ns on C4@100MHz)
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#
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# Assert dfi_wrdata_en and present the data
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# on dfi_wrdata_mask/dfi_wrdata in the same
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# cycle as the write command.
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#
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# Assert dfi_rddata_en in the same cycle as the read
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# command. The data will come back on dfi_rddata
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# 4 cycles later, along with the assertion of
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# dfi_rddata_valid.
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#
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# This PHY only supports CAS Latency 2.
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#
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from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.fhdl.specials import *
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from misoclib.sdram.bus.dfi import *
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from misoclib import sdram
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class GENSDRPHY(Module):
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def __init__(self, pads):
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a = flen(pads.a)
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ba = flen(pads.ba)
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d = flen(pads.dq)
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self.phy_settings = sdram.PhySettings(
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memtype="SDR",
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dfi_d=d,
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nphases=1,
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rdphase=0,
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wrphase=0,
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rdcmdphase=0,
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wrcmdphase=0,
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cl=2,
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read_latency=4,
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write_latency=0
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)
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self.dfi = Interface(a, ba, d)
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###
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#
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# Command/address
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#
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self.sync += [
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pads.a.eq(self.dfi.p0.address),
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pads.ba.eq(self.dfi.p0.bank),
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pads.cke.eq(self.dfi.p0.cke),
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pads.cas_n.eq(self.dfi.p0.cas_n),
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pads.ras_n.eq(self.dfi.p0.ras_n),
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pads.we_n.eq(self.dfi.p0.we_n)
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]
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if hasattr(pads, "cs_n"):
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self.sync += pads.cs_n.eq(self.dfi.p0.cs_n),
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#
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# DQ/DQS/DM data
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#
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sd_dq_out = Signal(d)
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drive_dq = Signal()
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self.sync += sd_dq_out.eq(self.dfi.p0.wrdata),
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self.specials += Tristate(pads.dq, sd_dq_out, drive_dq)
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self.sync += \
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If(self.dfi.p0.wrdata_en,
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pads.dm.eq(self.dfi.p0.wrdata_mask)
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).Else(
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pads.dm.eq(0)
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)
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sd_dq_in_ps = Signal(d)
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self.sync.sys_ps += sd_dq_in_ps.eq(pads.dq)
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self.sync += self.dfi.p0.rddata.eq(sd_dq_in_ps)
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#
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# DQ/DM control
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#
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d_dfi_wrdata_en = Signal()
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self.sync += d_dfi_wrdata_en.eq(self.dfi.p0.wrdata_en)
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self.comb += drive_dq.eq(d_dfi_wrdata_en)
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rddata_sr = Signal(4)
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self.comb += self.dfi.p0.rddata_valid.eq(rddata_sr[3])
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self.sync += rddata_sr.eq(Cat(self.dfi.p0.rddata_en, rddata_sr[:3]))
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