litex/misoclib/mem/litesata/example_designs
2015-05-01 20:45:02 +02:00
..
build litesata: fix permissions and imports 2015-03-04 00:46:24 +00:00
platforms litesata: pep8 (E302) 2015-04-13 15:12:39 +02:00
targets litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data). 2015-05-01 17:51:18 +02:00
test litescope: rename host directory to software (to be coherent with others cores) 2015-05-01 20:45:02 +02:00
make.py litesata: pep8 (E222) 2015-04-13 15:29:34 +02:00