72 lines
1.7 KiB
Python
72 lines
1.7 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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class ResolutionDetection(Module, AutoReg):
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def __init__(self, nbits=10):
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self.hsync = Signal()
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self.vsync = Signal()
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self.de = Signal()
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self._hres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
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self._vres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
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self._de_cycles = RegisterField(2*nbits, READ_ONLY, WRITE_ONLY)
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###
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# HRES/VRES
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hsync_r = Signal()
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vsync_r = Signal()
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p_hsync = Signal()
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p_vsync = Signal()
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self.sync.pix += [
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hsync_r.eq(self.hsync),
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vsync_r.eq(self.vsync),
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]
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self.comb += [
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p_hsync.eq(self.hsync & ~hsync_r),
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p_vsync.eq(self.vsync & ~vsync_r)
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]
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hcounter = Signal(nbits)
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vcounter = Signal(nbits)
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self.sync.pix += [
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If(p_hsync,
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hcounter.eq(0)
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).Elif(self.de,
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hcounter.eq(hcounter + 1)
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),
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If(p_vsync,
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vcounter.eq(0)
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).Elif(p_hsync,
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vcounter.eq(vcounter + 1)
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)
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]
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hcounter_st = Signal(nbits)
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vcounter_st = Signal(nbits)
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self.sync.pix += [
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If(p_hsync & (hcounter != 0), hcounter_st.eq(hcounter)),
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If(p_vsync & (vcounter != 0), vcounter_st.eq(vcounter))
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]
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self.specials += MultiReg(hcounter_st, self._hres.field.w)
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self.specials += MultiReg(vcounter_st, self._vres.field.w)
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# DE
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de_r = Signal()
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pn_de = Signal()
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self.sync.pix += de_r.eq(self.de)
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self.comb += pn_de.eq(~self.de & de_r)
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decounter = Signal(2*nbits)
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self.sync.pix += If(self.de,
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decounter.eq(decounter + 1)
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).Else(
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decounter.eq(0)
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)
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decounter_st = Signal(2*nbits)
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self.sync.pix += If(pn_de, decounter_st.eq(decounter))
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self.specials += MultiReg(decounter_st, self._de_cycles.field.w)
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