138 lines
3.1 KiB
C
138 lines
3.1 KiB
C
#include <stdio.h>
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#include <stdlib.h>
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#include <irq.h>
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#include <uart.h>
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#include <hw/dvisampler.h>
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static int d0, d1, d2;
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static void print_status(void)
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{
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printf("Ph: %4d %4d %4d // %d%d%d [%d %d %d] // %d // %dx%d // %d\n", d0, d1, d2,
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CSR_DVISAMPLER0_D0_CHAR_SYNCED,
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CSR_DVISAMPLER0_D1_CHAR_SYNCED,
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CSR_DVISAMPLER0_D2_CHAR_SYNCED,
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CSR_DVISAMPLER0_D0_CTL_POS,
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CSR_DVISAMPLER0_D1_CTL_POS,
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CSR_DVISAMPLER0_D2_CTL_POS,
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CSR_DVISAMPLER0_CHAN_SYNCED,
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(CSR_DVISAMPLER0_HRESH << 8) | CSR_DVISAMPLER0_HRESL,
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(CSR_DVISAMPLER0_VRESH << 8) | CSR_DVISAMPLER0_VRESL,
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(CSR_DVISAMPLER0_DECNT2 << 16) | (CSR_DVISAMPLER0_DECNT1 << 8) | CSR_DVISAMPLER0_DECNT0);
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}
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static void calibrate_delays(void)
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{
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CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_CAL;
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CSR_DVISAMPLER0_D1_DELAY_CTL = DVISAMPLER_DELAY_CAL;
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CSR_DVISAMPLER0_D2_DELAY_CTL = DVISAMPLER_DELAY_CAL;
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while(CSR_DVISAMPLER0_D0_DELAY_BUSY || CSR_DVISAMPLER0_D1_DELAY_BUSY || CSR_DVISAMPLER0_D2_DELAY_BUSY);
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CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_RST;
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CSR_DVISAMPLER0_D1_DELAY_CTL = DVISAMPLER_DELAY_RST;
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CSR_DVISAMPLER0_D2_DELAY_CTL = DVISAMPLER_DELAY_RST;
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CSR_DVISAMPLER0_D0_PHASE_RESET = 1;
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CSR_DVISAMPLER0_D1_PHASE_RESET = 1;
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CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
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d0 = d1 = d2 = 0;
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printf("Delays calibrated\n");
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}
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static void adjust_phase(void)
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{
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switch(CSR_DVISAMPLER0_D0_PHASE) {
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case DVISAMPLER_TOO_LATE:
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CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_DEC;
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d0--;
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CSR_DVISAMPLER0_D0_PHASE_RESET = 1;
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break;
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case DVISAMPLER_TOO_EARLY:
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CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_INC;
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d0++;
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CSR_DVISAMPLER0_D0_PHASE_RESET = 1;
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break;
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}
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switch(CSR_DVISAMPLER0_D1_PHASE) {
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case DVISAMPLER_TOO_LATE:
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CSR_DVISAMPLER0_D1_DELAY_CTL = DVISAMPLER_DELAY_DEC;
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d1--;
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CSR_DVISAMPLER0_D1_PHASE_RESET = 1;
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break;
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case DVISAMPLER_TOO_EARLY:
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CSR_DVISAMPLER0_D1_DELAY_CTL = DVISAMPLER_DELAY_INC;
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d1++;
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CSR_DVISAMPLER0_D1_PHASE_RESET = 1;
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break;
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}
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switch(CSR_DVISAMPLER0_D2_PHASE) {
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case DVISAMPLER_TOO_LATE:
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CSR_DVISAMPLER0_D2_DELAY_CTL = DVISAMPLER_DELAY_DEC;
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d2--;
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CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
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break;
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case DVISAMPLER_TOO_EARLY:
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CSR_DVISAMPLER0_D2_DELAY_CTL = DVISAMPLER_DELAY_INC;
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d2++;
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CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
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break;
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}
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}
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static int init_phase(void)
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{
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int od0, od1, od2;
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int i, j;
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for(i=0;i<100;i++) {
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od0 = d0;
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od1 = d1;
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od2 = d2;
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for(j=0;j<1000;j++)
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adjust_phase();
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if((abs(d0 - od0) < 4) && (abs(d1 - od1) < 4) && (abs(d2 - od2) < 4))
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return 1;
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}
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return 0;
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}
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static void vmix(void)
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{
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int i;
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unsigned int counter;
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while(1) {
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while(!CSR_DVISAMPLER0_PLL_LOCKED);
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printf("PLL locked\n");
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calibrate_delays();
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if(init_phase())
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printf("Phase init OK\n");
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else
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printf("Phase did not settle\n");
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print_status();
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counter = 0;
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while(CSR_DVISAMPLER0_PLL_LOCKED) {
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counter++;
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if(counter == 2000000) {
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print_status();
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//adjust_phase();
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counter = 0;
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}
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}
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printf("PLL unlocked\n");
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}
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}
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int main(void)
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{
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irq_setmask(0);
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irq_setie(1);
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uart_init();
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puts("Minimal video mixer software built "__DATE__" "__TIME__"\n");
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vmix();
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return 0;
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}
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