47 lines
1.2 KiB
Python
47 lines
1.2 KiB
Python
from migen.fhdl.structure import *
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from migen.bus import wishbone, wishbone2asmi, asmibus
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from migen.sim.generic import Simulator, TopLevel
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from milkymist.asmicon import *
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from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
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l2_size = 8192 # in bytes
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def my_generator():
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for x in range(20):
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t = TWrite(x, x)
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yield t
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print(str(t) + " delay=" + str(t.latency))
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for x in range(20):
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t = TRead(x)
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yield t
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print(str(t) + " delay=" + str(t.latency))
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for x in range(20):
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t = TRead(x+l2_size//4)
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yield t
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print(str(t) + " delay=" + str(t.latency))
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def main():
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controller = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
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bridge = wishbone2asmi.WB2ASMI(l2_size//4, controller.hub.get_port())
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controller.finalize()
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initiator = wishbone.Initiator(my_generator())
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conn = wishbone.InterconnectPointToPoint(initiator.bus, bridge.wishbone)
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logger = DFILogger(controller.dfi)
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def end_simulation(s):
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s.interrupt = initiator.done
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fragment = controller.get_fragment() + \
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bridge.get_fragment() + \
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initiator.get_fragment() + \
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conn.get_fragment() + \
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logger.get_fragment() + \
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Fragment(sim=[end_simulation])
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sim = Simulator(fragment, TopLevel("my.vcd"))
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sim.run()
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main()
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