111 lines
4.1 KiB
Python
111 lines
4.1 KiB
Python
# This file is Copyright (c) 2014 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.actorlib.fifo import AsyncFIFO
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from migen.actorlib.structuring import Converter, Pipeline
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from migen.bank.eventmanager import SharedIRQ
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from migen.bank.description import *
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from migen.fhdl.simplify import *
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from misoclib.ethmac.std import *
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from misoclib.ethmac.preamble import PreambleInserter, PreambleChecker
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from migen.actorlib.crc import CRC32Inserter, CRC32Checker
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from misoclib.ethmac.last_be import TXLastBE, RXLastBE
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from misoclib.ethmac.sram import SRAMWriter, SRAMReader
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class EthMAC(Module, AutoCSR):
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def __init__(self, phy, interface="wishbone", with_hw_preamble_crc=True, endianness="be"):
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# Preamble / CRC (optional)
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if with_hw_preamble_crc:
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self._hw_preamble_crc = CSRStatus(reset=1)
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# Preamble insert/check
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preamble_inserter = PreambleInserter(phy.dw)
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preamble_checker = PreambleChecker(phy.dw)
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self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
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self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
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# CRC insert/check
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crc32_inserter = CRC32Inserter(eth_description(phy.dw))
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crc32_checker = CRC32Checker(eth_description(phy.dw))
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self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
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self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
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# Delimiters
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tx_last_be = TXLastBE(phy.dw)
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rx_last_be = RXLastBE(phy.dw)
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self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
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self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
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# Converters
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reverse = endianness == "be"
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tx_converter = Converter(eth_description(32), eth_description(phy.dw), reverse=reverse)
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rx_converter = Converter(eth_description(phy.dw), eth_description(32), reverse=reverse)
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self.submodules += RenameClockDomains(tx_converter, "eth_tx")
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self.submodules += RenameClockDomains(rx_converter, "eth_rx")
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# Cross Domain Crossing
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tx_cdc = AsyncFIFO(eth_description(32), 4)
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rx_cdc = AsyncFIFO(eth_description(32), 4)
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self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
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self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
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# Graph
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if with_hw_preamble_crc:
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rx_pipeline = [phy, preamble_checker, crc32_checker, rx_last_be, rx_converter, rx_cdc]
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tx_pipeline = [tx_cdc, tx_converter, tx_last_be, crc32_inserter, preamble_inserter, phy]
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else:
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rx_pipeline = [phy, rx_last_be, rx_converter, rx_cdc]
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tx_pipeline = [tx_cdc, tx_converter, tx_last_be, phy]
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self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
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self.submodules.tx_pipeline = Pipeline(*tx_pipeline)
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if interface == "wishbone":
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nrxslots=2
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ntxslots=2
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self.bus = wishbone.Interface()
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# SRAM Memories
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sram_depth = buffer_depth//(32//8)
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self.submodules.sram_writer = SRAMWriter(sram_depth, nrxslots)
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self.submodules.sram_reader = SRAMReader(sram_depth, ntxslots)
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self.submodules.ev = SharedIRQ(self.sram_writer.ev, self.sram_reader.ev)
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# Connect to pipelines
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self.comb += [
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self.rx_pipeline.source.connect(self.sram_writer.sink),
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self.sram_reader.source.connect(self.tx_pipeline.sink)
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]
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# Interface
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wb_rx_sram_ifs = [wishbone.SRAM(self.sram_writer.mems[n], read_only=True)
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for n in range(nrxslots)]
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wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram_reader.mems[n], read_only=False))
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for n in range(ntxslots)]
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wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
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wb_slaves = []
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decoderoffset = log2_int(sram_depth)
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decoderbits = log2_int(len(wb_sram_ifs))
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for n, wb_sram_if in enumerate(wb_sram_ifs):
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def slave_filter(a, v=n):
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return a[decoderoffset:decoderoffset+decoderbits] == v
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wb_slaves.append((slave_filter, wb_sram_if.bus))
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self.submodules += wb_sram_if
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wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
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self.submodules += wb_con
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elif interface == "lasmi":
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raise NotImplementedError
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elif interface == "expose":
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# expose pipelines endpoints
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self.sink = tx_pipeline.sink
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self.source = rx_pipeline.source
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else:
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raise ValueError("EthMAC only supports Wishbone, LASMI or expose interfaces")
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