135 lines
3.2 KiB
Python
135 lines
3.2 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from misoclib.ethmac import EthMAC
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from misoclib.ethmac.phys import loopback
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class WishboneMaster():
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def __init__(self, obj):
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self.obj = obj
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self.dat = 0
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def write(self, adr, dat):
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self.obj.cyc = 1
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self.obj.stb = 1
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self.obj.adr = adr
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self.obj.we = 1
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self.obj.sel = 0xF
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self.obj.dat_w = dat
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while self.obj.ack == 0:
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yield
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self.obj.cyc = 0
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self.obj.stb = 0
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yield
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def read(self, adr):
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self.obj.cyc = 1
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self.obj.stb = 1
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self.obj.adr = adr
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self.obj.we = 0
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self.obj.sel = 0xF
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self.obj.dat_w = 0
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while self.obj.ack == 0:
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yield
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self.dat = self.obj.dat_r
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self.obj.cyc = 0
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self.obj.stb = 0
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yield
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class SRAMReaderDriver():
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def __init__(self, obj):
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self.obj = obj
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def start(self, slot, length):
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self.obj._slot.storage = slot
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self.obj._length.storage = length
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self.obj._start.re = 1
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yield
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self.obj._start.re = 0
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yield
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def wait_done(self):
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while self.obj.ev.done.pending == 0:
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yield
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def clear_done(self):
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self.obj.ev.done.clear = 1
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yield
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self.obj.ev.done.clear = 0
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yield
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class TB(Module):
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def __init__(self):
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self.submodules.ethphy = loopback.LoopbackPHY()
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self.submodules.ethmac = EthMAC(phy=self.ethphy, with_hw_preamble_crc=True)
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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wishbone_master = WishboneMaster(selfp.ethmac.bus)
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sram_reader_driver = SRAMReaderDriver(selfp.ethmac.sram_reader)
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sram_writer_slots_offset = [0x000, 0x200]
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sram_reader_slots_offset = [0x400, 0x600]
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length = 1500-2
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payload = [i%0xFF for i in range(length)] + [0, 0, 0, 0]
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errors = 0
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for slot in range(2):
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# fill tx memory
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for i in range(length//4+1):
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dat = 0
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dat |= payload[4*i+0] << 24
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dat |= payload[4*i+1] << 16
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dat |= payload[4*i+2] << 8
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dat |= payload[4*i+3] << 0
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yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
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# send tx data & wait
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yield from sram_reader_driver.start(slot, length)
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yield from sram_reader_driver.wait_done()
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yield from sram_reader_driver.clear_done()
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# get rx data (loopback on PHY Model)
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rx_dat = []
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for i in range(length//4+1):
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yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
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dat = wishbone_master.dat
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rx_dat.append((dat >> 24) & 0xFF)
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rx_dat.append((dat >> 16) & 0xFF)
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rx_dat.append((dat >> 8) & 0xFF)
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rx_dat.append((dat >> 0) & 0xFF)
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# check rx data
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for i in range(length):
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#print("%02x / %02x" %(rx_dat[i], payload[i]))
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if rx_dat[i] != payload[i]:
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errors += 1
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for i in range(200):
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yield
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#print(selfp.ethmac.sram_reader._length.storage)
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print("Errors : %d" %errors)
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=16000, vcd_name="my.vcd", keep_files=True)
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