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60ae9dce0d
litex
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examples
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sim
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Sebastien Bourdeauducq
a67b4baa0c
sim: VCD output support
2015-09-21 21:20:31 +08:00
..
basic1.py
sim: VCD output support
2015-09-21 21:20:31 +08:00
basic2.py
sim: VCD output support
2015-09-21 21:20:31 +08:00
fir.py
sim: VCD output support
2015-09-21 21:20:31 +08:00
memory.py
sim: VCD output support
2015-09-21 21:20:31 +08:00