34 lines
1.1 KiB
Python
34 lines
1.1 KiB
Python
import os
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from mibuild.platforms import de1
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from mibuild.altera_quartus import _add_period_constraint
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import top
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def main():
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plat = de1.Platform()
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soc = top.SoC()
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# set pin constraints
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plat.request("clk50", obj=soc.clk50)
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plat.request("key", obj=soc.key)
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plat.request("ledg", obj=soc.led)
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plat.request("gpio_0", obj=soc.gpio_0)
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# set extra constraints
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plat.add_platform_command("""
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name TOP_LEVEL_ENTITY "top"
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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""")
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_add_period_constraint(plat, "sys_clk", 20.0)
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cd = dict()
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cd["sys"] = soc.cd_sys
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plat.build_cmdline(soc.get_fragment(), clock_domains=cd)
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if __name__ == "__main__":
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main() |