104 lines
2.1 KiB
Python
104 lines
2.1 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.sim.generic import Simulator, PureSimulable, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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from miscope import trigger
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from miscope.tools.truthtable import *
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def term_prog(off, dat):
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for i in range(4):
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yield TWrite(off+3-i, (dat>>(8*i))&0xFF)
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def sum_prog(off, addr, dat):
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we = 2
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yield TWrite(off+3, addr%0xFF)
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yield TWrite(off+2, (addr>>8)%0xFF)
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yield TWrite(off+1, we+dat)
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yield TWrite(off+0, 0)
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for i in range(4):
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yield TWrite(off+i,0)
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csr_done = False
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def csr_transactions():
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term_trans = []
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term_trans += [term_prog(0x04 ,0xDEADBEEF)]
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term_trans += [term_prog(0x08 ,0xCAFEFADE)]
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term_trans += [term_prog(0x0C ,0xDEADBEEF)]
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term_trans += [term_prog(0x10 ,0xCAFEFADE)]
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for t in term_trans:
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for r in t:
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yield r
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sum_trans = []
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sum_trans += [sum_prog(0x00, i, 1) for i in range(8)]
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sum_trans += [sum_prog(0x00, i, 0) for i in range(8)]
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for t in sum_trans:
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for r in t:
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yield r
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sum_tt = gen_truth_table("i1 & i2 & i3 & i4")
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sum_trans = []
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for i in range(len(sum_tt)):
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sum_trans.append(sum_prog(0x00, i, sum_tt[i]))
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print(sum_tt)
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for t in sum_trans:
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for r in t:
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yield r
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global csr_done
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csr_done = True
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for t in range(100):
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yield None
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def main():
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# Csr Master
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csr_master0 = csr.Initiator(csr_transactions())
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# Trigger
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term0 = trigger.Term(32)
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term1 = trigger.Term(32)
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term2 = trigger.Term(32)
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term3 = trigger.Term(32)
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trigger0 = trigger.Trigger(0, 32, 64, [term0, term1, term2, term3])
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# Csr Interconnect
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csrcon0 = csr.Interconnect(csr_master0.bus,
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[
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trigger0.bank.interface
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])
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# Term Test
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def term_stimuli(s):
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if csr_done:
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s.wr(term0.i, 0xDEADBEEF)
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s.wr(term1.i ,0xCAFEFADE)
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s.wr(term2.i, 0xDEADBEEF)
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s.wr(term3.i, 0xCAFEFADE)
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# Simulation
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def end_simulation(s):
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s.interrupt = csr_master0.done
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fragment = autofragment.from_local()
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fragment += Fragment(sim=[end_simulation])
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fragment += Fragment(sim=[term_stimuli])
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sim = Simulator(fragment, Runner(), TopLevel("tb_TriggerCsr.vcd"))
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sim.run(2000)
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main()
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input()
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