110 lines
3.5 KiB
Python
110 lines
3.5 KiB
Python
import os
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone2csr
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from migen.bank.description import *
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from targets import *
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from misoclib.tools.litescope.common import *
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from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
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from misoclib.tools.litescope.frontend.io import LiteScopeIO
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from misoclib.tools.litescope.frontend.la import LiteScopeLA
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from misoclib.tools.litescope.core.port import LiteScopeTerm
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class _CRG(Module):
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def __init__(self, clk_in):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# Power on Reset (vendor agnostic)
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_sys.clk.eq(clk_in),
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self.cd_por.clk.eq(clk_in),
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self.cd_sys.rst.eq(~rst_n)
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]
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class SoC(Module):
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csr_base = 0x00000000
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csr_data_width = 32
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csr_map = {
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"bridge": 0,
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"identifier": 1,
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}
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interrupt_map = {}
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cpu_type = None
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def __init__(self, platform, clk_freq):
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self.clk_freq = clk_freq
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# UART <--> Wishbone bridge
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self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
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# CSR bridge 0x00000000 (shadow @0x00000000)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
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self._wb_masters = [self.uart2wb.wishbone]
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self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
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self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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# CSR
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self.submodules.identifier = Identifier(0, int(clk_freq))
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def add_cpu_memory_region(self, name, origin, length):
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self.cpu_memory_regions.append((name, origin, length))
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def add_cpu_csr_region(self, name, origin, busword, obj):
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self.cpu_csr_regions.append((name, origin, busword, obj))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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class LiteScopeSoC(SoC, AutoCSR):
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default_platform = "de0nano"
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csr_map = {
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"io": 10,
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"la": 11
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform):
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clk_freq = 50*1000000
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SoC.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform.request("clk50"))
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self.submodules.io = LiteScopeIO(8)
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self.leds = Cat(*[platform.request("user_led", i) for i in range(8)])
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self.comb += self.leds.eq(self.io.o)
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self.submodules.counter0 = counter0 = Counter(bits_sign=8)
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self.submodules.counter1 = counter1 = Counter(bits_sign=8)
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self.comb += [
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counter0.ce.eq(1),
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If(counter0.value == 16,
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counter0.reset.eq(1),
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counter1.ce.eq(1)
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)
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]
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self.debug = (
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counter1.value
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)
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self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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def do_exit(self, vns):
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self.la.export(vns, "test/la.csv")
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default_subtarget = LiteScopeSoC
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