Sebastien Bourdeauducq 29f7b94e37 bus/wishbone/sram: expose memory component		2013-11-24 23:43:14 +01:00
..
__init__.py	CSR bus definitions	2011-12-05 00:16:44 +01:00
csr.py	Better record layout parameterization mechanism	2013-10-23 12:54:50 +02:00
dfi.py	dfi: split phase description	2013-07-10 19:56:47 +02:00
lasmibus.py	lasmibus/Crossbar: more flexible master assignment	2013-11-23 17:51:22 +01:00
memory.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
transactions.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
wishbone.py	bus/wishbone/sram: expose memory component	2013-11-24 23:43:14 +01:00
wishbone2csr.py	csr: new data width API	2013-07-28 16:33:36 +02:00
wishbone2lasmi.py	bus/wb2lasmi: use existing interface to determine WB width to be consistent with other modules	2013-08-26 20:33:34 +02:00