82 lines
2.8 KiB
Python
82 lines
2.8 KiB
Python
from litescope.common import *
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from litescope.core.trigger import LiteScopeTrigger
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from litescope.core.storage import LiteScopeSubSampler, LiteScopeRecorder, LiteScopeRunLengthEncoder
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from mibuild.tools import write_to_file
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class LiteScopeLA(Module, AutoCSR):
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def __init__(self, layout, depth, clk_domain="sys",
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with_input_buffer=False, with_rle=False, with_subsampler=False):
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self.layout = layout
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self.data = Cat(*layout)
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self.dw = flen(self.data)
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self.depth = depth
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self.clk_domain = clk_domain
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self.with_rle = with_rle
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self.with_input_buffer = with_input_buffer
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self.with_subsampler = with_subsampler
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self.sink = Sink(data_layout(self.dw))
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self.comb += [
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self.sink.stb.eq(1),
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self.sink.data.eq(self.data)
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]
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self.submodules.trigger = trigger = LiteScopeTrigger(self.dw)
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self.submodules.recorder = recorder = LiteScopeRecorder(self.dw, self.depth)
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def do_finalize(self):
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sink = self.sink
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# insert Buffer on sink (optional, can be used to improve timings)
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if self.with_input_buffer:
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self.submodules.buffer = Buffer(self.sink.description)
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self.comb += Record.connect(sink, self.buffer.d)
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sink = self.buffer.q
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# clock domain crossing (optional, required when capture_clk is not sys_clk)
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# XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation
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if self.clk_domain is not "sys":
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self.submodules.fifo = AsyncFIFO(self.sink.description, 32)
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self.submodules += RenameClockDomains(self.fifo, {"write": self.clk_domain, "read": "sys"})
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self.comb += Record.connect(sink, self.fifo.sink)
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sink = self.fifo.source
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# connect trigger
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self.comb += [
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self.trigger.sink.stb.eq(sink.stb),
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self.trigger.sink.data.eq(sink.data),
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]
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# insert subsampler (optional)
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if self.with_subsampler:
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self.submodules.subsampler = LiteScopeSubSampler(self.dw)
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self.comb += Record.connect(sink, self.subsampler.sink)
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sink = self.subsampler.source
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# connect recorder
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self.comb += Record.connect(self.trigger.source, self.recorder.trigger_sink)
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if self.with_rle:
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rle = LiteScopeRunLengthEncoder(self.dw)
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self.submodules += rle
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self.comb += [
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Record.connect(sink, rle.sink),
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Record.connect(rle.source, self.recorder.data_sink)
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]
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else:
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self.submodules.delay_buffer = Buffer(self.sink.description)
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self.comb += [
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Record.connect(sink, self.delay_buffer.d),
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Record.connect(self.delay_buffer.q, self.recorder.data_sink)
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]
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def export(self, vns, filename):
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def format_line(*args):
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return ",".join(args) + "\n"
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r = ""
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r += format_line("config", "dw", str(self.dw))
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r += format_line("config", "depth", str(self.depth))
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r += format_line("config", "with_rle", str(int(self.with_rle)))
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for e in self.layout:
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r += format_line("layout", vns.get_name(e), str(flen(e)))
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write_to_file(filename, r)
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