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__init__.py
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add test directory with test_code_8b10b.py (from misoc)
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2017-04-24 18:46:55 +02:00 |
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test_avalon_mm.py
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Merge branch 'master' into avalon-burst-test
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2023-05-10 11:12:30 +02:00 |
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test_axi.py
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soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.
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2023-10-27 10:55:13 +02:00 |
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test_axi_lite.py
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soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.
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2023-10-27 10:55:13 +02:00 |
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test_axi_stream.py
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test: Add minimal test_axi_stream test (Just syntax check for now).
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2022-09-08 11:53:05 +02:00 |
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test_bitbang.py
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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test_clock.py
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cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.
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2022-01-25 11:09:15 +01:00 |
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test_code_8b10b.py
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soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).
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2020-10-21 09:29:21 +02:00 |
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test_cpu.py
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test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated).
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2024-05-14 12:53:09 +02:00 |
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test_csr.py
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csr_bus: Honour re signal from the upstream bus
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2024-06-23 19:35:19 +01:00 |
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test_ecc.py
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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test_emif.py
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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test_fifosyncmacro.py
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test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow
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2022-06-17 16:27:25 +02:00 |
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test_gearbox.py
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inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.
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2021-03-18 13:47:10 +01:00 |
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test_hyperbus.py
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soc/cores/hyperbus: Add automatic read burst detection.
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2024-08-30 11:53:14 +02:00 |
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test_i2c.py
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test_i2c: whitespace cleanups
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2024-07-20 15:45:44 +10:00 |
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test_i2s.py
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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test_icap.py
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cores/icap/ICAP: Add Register read capability.
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2021-10-04 17:22:57 +02:00 |
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test_led.py
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Fixes #2103: calculate memory depth for WS2812
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2024-10-25 11:48:57 +08:00 |
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test_packet.py
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test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.
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2021-10-23 17:40:41 +02:00 |
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test_prbs.py
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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test_reduce.py
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gen/common/Reduce: Add ADD support.
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2022-10-28 19:13:27 +02:00 |
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test_spi.py
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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test_spi_mmap.py
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test/spi_mmap: be less verbose
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2024-04-05 12:35:47 +11:00 |
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test_spi_opi.py
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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test_stream.py
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stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.
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2022-09-07 08:59:37 +02:00 |
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test_timer.py
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test/test_timer: Update.
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2021-05-27 19:37:51 +02:00 |
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test_wishbone.py
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test/test_wishbone: Improve origin_region_remap_test to test more complex remapping.
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2024-02-28 19:11:55 +01:00 |
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