61 lines
1.9 KiB
Python
61 lines
1.9 KiB
Python
import unittest
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import subprocess
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import os
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from migen.fhdl.std import *
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from migen.fhdl.verilog import convert
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# Create a module with some combinatorial, some sequential, and some simple
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# assigns
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class SyntaxModule(Module):
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def __init__(self):
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x = [Signal(8) for y in range(10)]
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y = [Signal(8) for z in range(10)]
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en = Signal()
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a = Signal()
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b = Signal()
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z = Signal()
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as_src = Signal(16);
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as_tgt1 = Signal(16);
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as_tgt2 = Signal(16);
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self.io = {a, b, z, en, as_src, as_tgt1, as_tgt2}
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self.comb += If(a, z.eq(b))
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self.comb += as_tgt1.eq(as_src)
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self.comb += as_tgt2.eq(100)
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for xi in x:
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self.io.add(xi)
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for xi in range(1, len(x)):
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self.comb += If(en, y[xi].eq(x[xi-1])).Else(y[xi].eq(x[xi]))
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self.sync += x[xi].eq(y[xi])
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# Create unit test to build module, run Verilator and check for errors
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class SyntaxCase(unittest.TestCase):
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def base_test(self, name, asic_syntax, options=[]):
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filename = "test_module_{}.v".format(name)
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t = SyntaxModule()
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c = convert(t, t.io, name="test_module", asic_syntax=asic_syntax)
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f = open(filename, "w")
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f.write(str(c))
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f.close()
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subprocess.check_call("verilator --lint-only " + " ".join(options) + " " + filename,
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stdout=subprocess.DEVNULL,
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stderr=subprocess.DEVNULL, shell=True)
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os.unlink(filename)
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def test_generic_syntax(self):
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options = [
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"-Wno-WIDTH",
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"-Wno-COMBDLY",
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"-Wno-INITIALDLY"
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]
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self.base_test("generic", False, options)
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def test_asic_syntax(self):
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options = [
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"-Wno-WIDTH", # XXX should we improve ASIC backend to remove this?
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]
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self.base_test("asic", True, options)
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