215 lines
5.0 KiB
Coq
215 lines
5.0 KiB
Coq
/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2011, 2012 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module tb_conbus();
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reg sys_rst;
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reg sys_clk;
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//------------------------------------------------------------------
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// Wishbone master wires
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//------------------------------------------------------------------
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wire [29:0] m1_wishbone_adr,
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m2_wishbone_adr;
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wire [31:0] m1_wishbone_dat_r,
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m1_wishbone_dat_w,
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m2_wishbone_dat_r,
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m2_wishbone_dat_w;
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wire [3:0] m1_wishbone_sel,
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m2_wishbone_sel;
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wire m1_wishbone_we,
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m2_wishbone_we;
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wire m1_wishbone_cyc,
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m2_wishbone_cyc;
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wire m1_wishbone_stb,
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m2_wishbone_stb;
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wire m1_wishbone_ack,
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m2_wishbone_ack;
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//------------------------------------------------------------------
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// Wishbone slave wires
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//------------------------------------------------------------------
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wire [29:0] s1_wishbone_adr,
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s2_wishbone_adr;
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wire [31:0] s1_wishbone_dat_r,
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s1_wishbone_dat_w,
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s2_wishbone_dat_r,
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s2_wishbone_dat_w;
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wire [3:0] s1_wishbone_sel,
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s2_wishbone_sel;
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wire s1_wishbone_we,
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s2_wishbone_we;
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wire s1_wishbone_cyc,
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s2_wishbone_cyc;
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wire s1_wishbone_stb,
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s2_wishbone_stb;
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wire s1_wishbone_ack,
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s2_wishbone_ack;
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//---------------------------------------------------------------------------
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// Wishbone switch
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//---------------------------------------------------------------------------
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intercon dut(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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// Master 0
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.m1_wishbone_dat_o(m1_wishbone_dat_w),
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.m1_wishbone_dat_i(m1_wishbone_dat_r),
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.m1_wishbone_adr_o(m1_wishbone_adr),
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.m1_wishbone_we_o(m1_wishbone_we),
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.m1_wishbone_sel_o(m1_wishbone_sel),
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.m1_wishbone_cyc_o(m1_wishbone_cyc),
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.m1_wishbone_stb_o(m1_wishbone_stb),
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.m1_wishbone_ack_i(m1_wishbone_ack),
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// Master 1
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.m2_wishbone_dat_o(m2_wishbone_dat_w),
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.m2_wishbone_dat_i(m2_wishbone_dat_r),
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.m2_wishbone_adr_o(m2_wishbone_adr),
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.m2_wishbone_we_o(m2_wishbone_we),
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.m2_wishbone_sel_o(m2_wishbone_sel),
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.m2_wishbone_cyc_o(m2_wishbone_cyc),
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.m2_wishbone_stb_o(m2_wishbone_stb),
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.m2_wishbone_ack_i(m2_wishbone_ack),
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// Slave 0
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.s1_wishbone_dat_o(s1_wishbone_dat_r),
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.s1_wishbone_dat_i(s1_wishbone_dat_w),
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.s1_wishbone_adr_i(s1_wishbone_adr),
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.s1_wishbone_sel_i(s1_wishbone_sel),
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.s1_wishbone_we_i(s1_wishbone_we),
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.s1_wishbone_cyc_i(s1_wishbone_cyc),
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.s1_wishbone_stb_i(s1_wishbone_stb),
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.s1_wishbone_ack_o(s1_wishbone_ack),
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// Slave 1
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.s2_wishbone_dat_o(s2_wishbone_dat_r),
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.s2_wishbone_dat_i(s2_wishbone_dat_w),
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.s2_wishbone_adr_i(s2_wishbone_adr),
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.s2_wishbone_sel_i(s2_wishbone_sel),
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.s2_wishbone_we_i(s2_wishbone_we),
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.s2_wishbone_cyc_i(s2_wishbone_cyc),
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.s2_wishbone_stb_i(s2_wishbone_stb),
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.s2_wishbone_ack_o(s2_wishbone_ack)
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);
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//---------------------------------------------------------------------------
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// Masters
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//---------------------------------------------------------------------------
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wire m1_wishbone_end;
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master #(
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.id(0)
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) m0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(m1_wishbone_dat_w),
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.dat_r(m1_wishbone_dat_r),
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.adr(m1_wishbone_adr),
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.we(m1_wishbone_we),
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.sel(m1_wishbone_sel),
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.cyc(m1_wishbone_cyc),
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.stb(m1_wishbone_stb),
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.ack(m1_wishbone_ack),
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.tend(m1_wishbone_end)
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);
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wire m2_wishbone_end;
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master #(
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.id(1)
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) m1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(m2_wishbone_dat_w),
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.dat_r(m2_wishbone_dat_r),
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.adr(m2_wishbone_adr),
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.we(m2_wishbone_we),
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.sel(m2_wishbone_sel),
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.cyc(m2_wishbone_cyc),
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.stb(m2_wishbone_stb),
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.ack(m2_wishbone_ack),
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.tend(m2_wishbone_end)
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);
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//---------------------------------------------------------------------------
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// Slaves
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//---------------------------------------------------------------------------
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slave #(
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.id(0)
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) s0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(s1_wishbone_dat_w),
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.dat_r(s1_wishbone_dat_r),
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.adr(s1_wishbone_adr),
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.we(s1_wishbone_we),
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.sel(s1_wishbone_sel),
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.cyc(s1_wishbone_cyc),
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.stb(s1_wishbone_stb),
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.ack(s1_wishbone_ack)
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);
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slave #(
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.id(1)
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) s1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(s2_wishbone_dat_w),
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.dat_r(s2_wishbone_dat_r),
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.adr(s2_wishbone_adr),
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.we(s2_wishbone_we),
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.sel(s2_wishbone_sel),
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.cyc(s2_wishbone_cyc),
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.stb(s2_wishbone_stb),
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.ack(s2_wishbone_ack)
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);
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initial sys_clk = 1'b0;
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always #5 sys_clk = ~sys_clk;
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wire all_end = m1_wishbone_end & m2_wishbone_end;
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always begin
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$dumpfile("intercon.vcd");
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$dumpvars(1, dut);
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sys_rst = 1'b1;
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@(posedge sys_clk);
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#1 sys_rst = 1'b0;
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@(posedge all_end);
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$finish;
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end
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endmodule
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