325 lines
8.5 KiB
Python
325 lines
8.5 KiB
Python
from litesata.common import *
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tx_to_rx = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("count", 16)
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]
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rx_to_tx = [
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("dma_activate", 1),
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("d2h_error", 1)
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]
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class LiteSATACommandTX(Module):
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def __init__(self, transport):
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self.sink = sink = Sink(command_tx_description(32))
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self.to_rx = to_rx = Source(tx_to_rx)
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self.from_rx = from_rx = Sink(rx_to_tx)
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###
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self.comb += [
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transport.sink.pm_port.eq(0),
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transport.sink.features.eq(0),
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transport.sink.lba.eq(sink.sector),
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transport.sink.device.eq(0xe0),
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transport.sink.count.eq(sink.count),
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transport.sink.icc.eq(0),
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transport.sink.control.eq(0),
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transport.sink.data.eq(sink.data)
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]
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self.dwords_counter = dwords_counter = Counter(max=fis_max_dwords)
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identify = Signal()
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(0),
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If(sink.stb & sink.sop,
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If(sink.write,
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NextState("SEND_WRITE_DMA_CMD")
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).Elif(sink.read,
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NextState("SEND_READ_DMA_OR_IDENTIFY_CMD")
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).Else(
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sink.ack.eq(1)
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)
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).Else(
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sink.ack.eq(1)
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)
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)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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identify.eq(sink.identify)
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)
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fsm.act("SEND_WRITE_DMA_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["WRITE_DMA_EXT"]),
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If(sink.stb & transport.sink.ack,
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NextState("WAIT_DMA_ACTIVATE")
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)
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)
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fsm.act("WAIT_DMA_ACTIVATE",
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dwords_counter.reset.eq(1),
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If(from_rx.dma_activate,
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NextState("SEND_DATA")
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).Elif(from_rx.d2h_error,
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sink.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("SEND_DATA",
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dwords_counter.ce.eq(sink.stb & sink.ack),
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(dwords_counter.value == 0),
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transport.sink.eop.eq((dwords_counter.value == (fis_max_dwords-1)) | sink.eop),
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transport.sink.type.eq(fis_types["DATA"]),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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If(sink.eop,
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NextState("IDLE")
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).Elif(dwords_counter.value == (fis_max_dwords-1),
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NextState("WAIT_DMA_ACTIVATE")
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)
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)
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)
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fsm.act("SEND_READ_DMA_OR_IDENTIFY_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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If(identify,
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transport.sink.command.eq(regs["IDENTIFY_DEVICE"]),
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).Else(
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transport.sink.command.eq(regs["READ_DMA_EXT"])
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),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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NextState("IDLE")
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)
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)
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self.comb += [
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If(sink.stb,
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to_rx.write.eq(sink.write),
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to_rx.read.eq(sink.read),
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to_rx.identify.eq(sink.identify),
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to_rx.count.eq(sink.count)
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)
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]
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class LiteSATACommandRX(Module):
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def __init__(self, transport):
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self.source = source = Source(command_rx_description(32))
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self.to_tx = to_tx = Source(rx_to_tx)
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self.from_tx = from_tx = Sink(tx_to_rx)
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###
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cmd_buffer = Buffer(command_rx_cmd_description(32))
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cmd_buffer.sink, cmd_buffer.source = cmd_buffer.d, cmd_buffer.q
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data_buffer = InsertReset(SyncFIFO(command_rx_data_description(32), fis_max_dwords, buffered=True))
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self.submodules += cmd_buffer, data_buffer
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def test_type(name):
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return transport.source.type == fis_types[name]
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identify = Signal()
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dma_activate = Signal()
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read_ndwords = Signal(max=sectors2dwords(2**16))
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self.dwords_counter = dwords_counter = Counter(max=sectors2dwords(2**16))
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read_done = Signal()
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self.sync += \
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If(from_tx.read,
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read_ndwords.eq(from_tx.count*sectors2dwords(1)-1)
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)
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self.comb += read_done.eq(self.dwords_counter.value == read_ndwords)
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d2h_error = Signal()
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clr_d2h_error = Signal()
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set_d2h_error = Signal()
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self.sync += \
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If(clr_d2h_error,
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d2h_error.eq(0)
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).Elif(set_d2h_error,
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d2h_error.eq(1)
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)
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.dwords_counter.reset.eq(1),
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transport.source.ack.eq(1),
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clr_d2h_error.eq(1),
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If(from_tx.write,
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NextState("WAIT_WRITE_ACTIVATE_OR_REG_D2H")
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).Elif(from_tx.read,
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NextState("WAIT_READ_DATA_OR_REG_D2H"),
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).Elif(from_tx.identify,
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NextState("WAIT_PIO_SETUP_D2H"),
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)
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)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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identify.eq(from_tx.identify)
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)
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fsm.act("WAIT_WRITE_ACTIVATE_OR_REG_D2H",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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If(test_type("DMA_ACTIVATE_D2H"),
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dma_activate.eq(1),
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).Elif(test_type("REG_D2H"),
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set_d2h_error.eq(transport.source.status[reg_d2h_status["err"]]),
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NextState("PRESENT_WRITE_RESPONSE")
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)
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)
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)
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fsm.act("PRESENT_WRITE_RESPONSE",
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cmd_buffer.sink.stb.eq(1),
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cmd_buffer.sink.write.eq(1),
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cmd_buffer.sink.last.eq(1),
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cmd_buffer.sink.success.eq(~transport.source.error & ~d2h_error),
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cmd_buffer.sink.failed.eq(transport.source.error | d2h_error),
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If(cmd_buffer.sink.stb & cmd_buffer.sink.ack,
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NextState("IDLE")
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)
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)
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fsm.act("WAIT_READ_DATA_OR_REG_D2H",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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transport.source.ack.eq(0),
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If(test_type("DATA"),
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NextState("PRESENT_READ_DATA")
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).Elif(test_type("REG_D2H"),
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set_d2h_error.eq(transport.source.status[reg_d2h_status["err"]]),
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NextState("PRESENT_READ_RESPONSE")
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)
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)
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)
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fsm.act("WAIT_PIO_SETUP_D2H",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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transport.source.ack.eq(0),
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If(test_type("PIO_SETUP_D2H"),
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NextState("PRESENT_PIO_SETUP_D2H")
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)
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)
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)
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fsm.act("PRESENT_PIO_SETUP_D2H",
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transport.source.ack.eq(1),
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If(transport.source.stb & transport.source.eop,
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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)
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)
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self.comb += [
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data_buffer.sink.sop.eq(transport.source.sop),
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data_buffer.sink.eop.eq(transport.source.eop),
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data_buffer.sink.data.eq(transport.source.data)
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]
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fsm.act("PRESENT_READ_DATA",
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data_buffer.sink.stb.eq(transport.source.stb),
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transport.source.ack.eq(data_buffer.sink.ack),
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If(data_buffer.sink.stb & data_buffer.sink.ack,
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self.dwords_counter.ce.eq(~read_done),
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If(data_buffer.sink.eop,
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If(read_done & ~identify,
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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).Else(
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NextState("PRESENT_READ_RESPONSE")
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)
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)
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)
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)
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read_error = Signal()
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self.sync += \
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If(fsm.before_entering("PRESENT_READ_DATA"),
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read_error.eq(1)
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).Elif(transport.source.stb & transport.source.ack & transport.source.eop,
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read_error.eq(transport.source.error)
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)
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fsm.act("PRESENT_READ_RESPONSE",
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cmd_buffer.sink.stb.eq(1),
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cmd_buffer.sink.read.eq(~identify),
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cmd_buffer.sink.identify.eq(identify),
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cmd_buffer.sink.last.eq(read_done | identify),
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cmd_buffer.sink.success.eq(~read_error & ~d2h_error),
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cmd_buffer.sink.failed.eq(read_error | d2h_error),
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If(cmd_buffer.sink.stb & cmd_buffer.sink.ack,
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If(cmd_buffer.sink.failed,
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data_buffer.reset.eq(1)
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),
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If(read_done | identify,
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NextState("IDLE")
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).Else(
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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)
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)
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)
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self.out_fsm = out_fsm = FSM(reset_state="IDLE")
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out_fsm.act("IDLE",
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If(cmd_buffer.source.stb,
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If((cmd_buffer.source.read | cmd_buffer.source.identify) & cmd_buffer.source.success,
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NextState("PRESENT_RESPONSE_WITH_DATA"),
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).Else(
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NextState("PRESENT_RESPONSE_WITHOUT_DATA"),
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)
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)
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)
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self.comb += [
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source.write.eq(cmd_buffer.source.write),
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source.read.eq(cmd_buffer.source.read),
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source.identify.eq(cmd_buffer.source.identify),
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source.last.eq(cmd_buffer.source.last),
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source.success.eq(cmd_buffer.source.success),
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source.failed.eq(cmd_buffer.source.failed),
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source.data.eq(data_buffer.source.data)
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]
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out_fsm.act("PRESENT_RESPONSE_WITH_DATA",
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source.stb.eq(data_buffer.source.stb),
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source.sop.eq(data_buffer.source.sop),
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source.eop.eq(data_buffer.source.eop),
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data_buffer.source.ack.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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cmd_buffer.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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out_fsm.act("PRESENT_RESPONSE_WITHOUT_DATA",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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If(source.stb & source.ack,
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cmd_buffer.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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self.comb += [
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to_tx.dma_activate.eq(dma_activate),
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to_tx.d2h_error.eq(d2h_error)
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]
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class LiteSATACommand(Module):
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def __init__(self, transport):
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self.tx = LiteSATACommandTX(transport)
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self.rx = LiteSATACommandRX(transport)
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self.comb += [
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self.rx.to_tx.connect(self.tx.from_rx),
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self.tx.to_rx.connect(self.rx.from_tx)
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]
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self.sink, self.source = self.tx.sink, self.rx.source
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