Greg Davill 642c4b3036 build/trellis: add verilog_read -defer option to yosys script		2020-04-27 20:10:25 +09:30
..
boards	targets/kcu105: use cmd_latency=1.	2020-04-25 12:12:27 +02:00
build	build/trellis: add verilog_read -defer option to yosys script	2020-04-27 20:10:25 +09:30
gen	litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.	2020-04-10 08:47:07 +02:00
soc	bios/sdram: reduce number of scan loops during cdly scan to speed it up.	2020-04-25 12:51:33 +02:00
tools	Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings	2020-04-25 08:27:00 +02:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00