227 lines
7.7 KiB
Python
Executable File
227 lines
7.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of MiSoC and has been adapted/modified for Litex.
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#
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# Copyright 2007-2023 / M-Labs Ltd
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# Copyright 2012-2015 / Enjoy-Digital
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# Copyright from Misoc LICENCE file added above
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#
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# Copyright 2023 Andrew Dennison <andrew@motec.com.au>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from migen.fhdl.specials import Tristate
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from litex.soc.cores.i2c import *
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class _MockPads:
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def __init__(self):
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self.scl = Signal()
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self.sda = Signal()
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class _MockTristateImpl(Module):
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def __init__(self, t):
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t.i_mock = Signal(reset=True)
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self.comb += [
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If(t.oe,
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t.target.eq(t.o),
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t.i.eq(t.o),
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).Else(
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t.target.eq(t.i_mock),
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t.i.eq(t.i_mock),
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),
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]
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class _MockTristate:
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"""A mock `Tristate` for simulation
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This simulation ensures the TriState input (_i) tracks the output (_o) when output enable
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(_oe) = 1. A new i_mock `Signal` is added - this can be written to in the simulation to represent
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input from the external device.
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Example usage:
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class TestMyModule(unittest.TestCase):
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def test_mymodule(self):
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dut = MyModule()
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io = Signal()
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dut.io_t = TSTriple()
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self.io_tristate = self.io_t.get_tristate(io)
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dut.comb += [
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dut.io_t.oe.eq(signal_for_oe),
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dut.io_t.o.eq(signal_for_o),
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signal_for_i.eq(dut.io_t.i),
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]
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def generator()
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yield dut.io_tristate.i_mock.eq(some_value)
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if (yield dut.io_t.oe):
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self.assertEqual((yield dut.scl_t.i), (yield dut.io_t.o))
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else:
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self.assertEqual((yield dut.scl_t.i), some_value)
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"""
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@staticmethod
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def lower(t):
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return _MockTristateImpl(t)
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class TestI2C(unittest.TestCase):
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def test_i2c(self):
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pads = _MockPads()
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dut = I2CMaster(pads)
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def check_trans(scl, sda, msg=""):
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scl, sda = int(scl), int(sda)
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scl_init, sda_init = (yield dut.scl_t.i), (yield dut.sda_t.i)
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timeout = 0
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while True:
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scl_now, sda_now = (yield dut.scl_t.i), (yield dut.sda_t.i)
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if scl_now == scl and sda_now == sda:
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return
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timeout += 1
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self.assertLess(timeout, 20,
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f"\n*** {msg} timeout. Waiting for: " +
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f"scl:{scl_now} checking:{scl_init}=>{scl} " +
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f"sda:{sda_now} checking:{sda_init}=>{sda} ***"
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)
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yield
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def wait_idle(do=lambda: ()):
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timeout = 0
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while True:
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timeout += 1
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self.assertLess(timeout, 20)
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idle = ((yield from dut.bus.read(I2C_XFER_ADDR)) & I2C_IDLE) != 0
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if idle:
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return
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yield
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def write_bit(value):
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#print(f"write_bit:{value}")
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yield from check_trans(scl=False, sda=value)
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yield from check_trans(scl=True, sda=value)
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def write_ack(value):
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#print(f"write_ack:{value}")
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yield from check_trans(scl=False, sda=not value)
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yield from check_trans(scl=True, sda=not value)
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yield from wait_idle()
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def read_bit(value):
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print(f"read_bit:{value}")
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yield dut.sda_tristate.i_mock.eq(value)
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yield from check_trans(scl=True, sda=value)
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yield from check_trans(scl=False, sda=value)
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yield dut.sda_tristate.i_mock.eq(True)
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def read_ack(value):
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#print(f"read_ack:{value}")
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yield from check_trans(scl=False, sda=True)
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yield dut.sda_tristate.i_mock.eq(not value)
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yield from check_trans(scl=True, sda=not value)
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yield from wait_idle()
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yield dut.sda_tristate.i_mock.eq(True)
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ack = ((yield from dut.bus.read(I2C_XFER_ADDR)) & I2C_ACK) != 0
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self.assertEqual(ack, value)
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def i2c_restart():
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yield from check_trans(scl=False, sda=True, msg="checking restart precondition")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START)
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yield from check_trans(scl=False, sda=True, msg="checking restart0")
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yield from check_trans(scl=True, sda=True, msg="checking restart1")
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yield from check_trans(scl=True, sda=False, msg="checking start0")
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yield from wait_idle()
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def i2c_start():
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yield from check_trans(scl=True, sda=True, msg="checking start precondition")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START)
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yield from check_trans(scl=True, sda=False, msg="checking start0")
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yield from wait_idle()
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def i2c_stop():
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yield from check_trans(scl=False, sda=True, msg="checking stop after read or write")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_STOP)
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yield from check_trans(scl=False, sda=False, msg="checking STOP0")
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yield from check_trans(scl=True, sda=False, msg="checking STOP1")
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yield from check_trans(scl=True, sda=True, msg="checking STOP2")
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yield from wait_idle()
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def i2c_write(value, ack=True):
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value = int(value)
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test_bin = '{0:08b}'.format(value)
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#print(f"I2C_WRITE | {hex(value)}:0x{test_bin}")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_WRITE | value)
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for i in list(test_bin):
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yield from write_bit(int(i))
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yield from read_ack(True)
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def i2c_read(value, ack=True):
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value = int(value)
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test_bin = '{0:08b}'.format(value)
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print(f"I2C_READ | {hex(value)}:0x{test_bin}")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_READ | (I2C_ACK if ack else 0))
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for i in list(test_bin):
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yield from read_bit(int(i))
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yield dut.sda_tristate.i_mock.eq(True)
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data = (yield from dut.bus.read(I2C_XFER_ADDR)) & 0xff
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self.assertEqual(data, value)
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yield from write_ack(ack)
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def check():
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yield from dut.bus.write(I2C_CONFIG_ADDR, 4)
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data = (yield from dut.bus.read(I2C_CONFIG_ADDR)) & 0xff
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self.assertEqual(data, 4)
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print("write 1 byte 0x18 to address 0x41")
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yield from i2c_start()
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yield from i2c_write(0x41<<1 | 0)
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yield from i2c_write(0x18, ack=False)
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yield from i2c_stop()
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print("read 1 byte from address 0x41")
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yield from i2c_start()
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yield from i2c_write(0x41<<1 | 1)
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yield from i2c_read(0x18, ack=False)
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print("write 2 bytes 0x10 0x00 to address 0x11")
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yield from i2c_restart()
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yield from i2c_write(0x11 << 1 | 0)
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yield from i2c_write(0x10, ack=True)
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yield from i2c_write(0x00, ack=False)
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yield from i2c_stop()
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print("read 1 byte from address 0x11")
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yield from i2c_start()
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yield from i2c_write(0x11 << 1 | 1)
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yield from i2c_read(0x81, ack=False)
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print("read 2 bytes from address 0x55")
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yield from i2c_restart()
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yield from i2c_write(0x55<<1 | 1)
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yield from i2c_read(0xDE, ack=True)
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yield from i2c_read(0xAD, ack=False)
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yield from i2c_stop()
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clocks = {
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"sys": 10,
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"async": (10, 3),
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}
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generators = {
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"sys": [
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check(),
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],
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}
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run_simulation(dut, generators, clocks, special_overrides={Tristate: _MockTristate}, vcd_name="i2c.vcd")
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if __name__ == "__main__":
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unittest.main()
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