Florent Kermarrec 6576416b8e cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. ... Useful for current tests with LiteSDCard using DMA and that requires the DMA to be connnected to the DMA bus of Rocket when the direct memory bus is used.		2020-07-29 09:35:15 +02:00
..
cores	cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing.	2020-07-29 09:35:15 +02:00
doc	litex: add sphinx_extra_config to generate_docs()	2020-07-24 16:01:54 +08:00
integration	integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone).	2020-07-27 19:57:29 +02:00
interconnect	soc/interconnect/axi: add basic AXI Lite up-converter	2020-07-24 13:47:18 +02:00
software	liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.	2020-07-28 14:36:49 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00