124 lines
3.1 KiB
Python
124 lines
3.1 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from lib.sata.std import *
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from lib.sata.transport.std import *
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regs = {
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"WRITE_DMA_EXT" : 0x35,
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"READ_DMA_EXT" : 0x25,
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"IDENTIFY_DEVICE_DMA" : 0xEE
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}
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from_rx = [
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("dma_activate", 1)
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]
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class SATACommandTX(Module):
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def __init__(self, transport):
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self.sink = sink = Sink(command_tx_layout(32))
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self.from_rx = Sink(from_rx)
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###
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self.comb += [
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transport.sink.pm_port.eq(0),
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transport.sink.features.eq(0),
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transport.sink.lba.eq(sink.address), # XXX need adaptation?
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transport.sink.device.eq(0xe0),
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transport.sink.count.eq(sink.length), # XXX need adaptation?
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transport.sink.icc.eq(0),
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transport.sink.control.eq(0),
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(sink.stb & sink.sop,
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If(sink.write,
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NextState("SEND_WRITE_DMA_CMD")
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).Elif(sink.read,
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NextState("SEND_READ_DMA_CMD")
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).Elif(sink.identify,
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NextState("SEND_IDENTIFY_CMD")
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).Else(
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sink.ack.eq(1)
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)
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).Else(
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sink.ack.eq(1)
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)
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)
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fsm.act("SEND_WRITE_DMA_CMD",
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transport.sink.stb.eq(1),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["WRITE_DMA_EXT"]),
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If(transport.sink.ack,
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NextState("WAIT_DMA_ACTIVATE")
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)
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)
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fsm.act("WAIT_DMA_ACTIVATE",
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If(self.from_rx.dma_activate,
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NextState("SEND_DATA")
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)
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)
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fsm.act("SEND_DATA",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(sink.sop),
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transport.sink.eop.eq(sink.eop),
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transport.sink.type.eq(fis_types["DATA"]),
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transport.sink.data.eq(sink.data),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack & sink.eop,
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NextState("IDLE")
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)
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)
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fsm.act("SEND_READ_DMA_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["READ_DMA_EXT"]),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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NextState("IDLE")
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)
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)
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fsm.act("SEND_IDENTIFY_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["IDENTIFY_DEVICE_DMA"]),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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NextState("IDLE")
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)
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)
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class SATACommandRX(Module):
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def __init__(self, transport):
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self.source = source = Source(command_tx_layout(32))
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self.to_tx = Source(from_rx)
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###
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self.comb += [
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transport.source.ack.eq(1),
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If(transport.source.stb & (transport.source.type == fis_types["DMA_ACTIVATE_D2H"]),
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self.to_tx.dma_activate.eq(1)
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)
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]
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class SATACommand(Module):
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def __init__(self, transport):
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self.submodules.tx = SATACommandTX(transport)
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self.submodules.rx = SATACommandRX(transport)
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self.sink, self.source = self.tx.sink, self.rx.source
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self.comb += self.rx.to_tx.connect(self.tx.from_rx)
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