163 lines
5.1 KiB
Python
163 lines
5.1 KiB
Python
from migen import *
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from migen.genlib.record import Record
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr_eventmanager import *
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from misoc.interconnect.stream import Source, Sink, SyncFIFO, AsyncFIFO
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class RS232PHYRX(Module):
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def __init__(self, pads, tuning_word):
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self.source = Source([("data", 8)])
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# # #
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uart_clk_rxen = Signal()
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phase_accumulator_rx = Signal(32)
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rx = Signal()
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self.specials += MultiReg(pads.rx, rx)
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rx_r = Signal()
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rx_reg = Signal(8)
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rx_bitcount = Signal(4)
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rx_busy = Signal()
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rx_done = self.source.stb
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rx_data = self.source.data
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self.sync += [
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rx_done.eq(0),
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rx_r.eq(rx),
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If(~rx_busy,
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If(~rx & rx_r, # look for start bit
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rx_busy.eq(1),
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rx_bitcount.eq(0),
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)
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).Else(
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If(uart_clk_rxen,
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rx_bitcount.eq(rx_bitcount + 1),
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If(rx_bitcount == 0,
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If(rx, # verify start bit
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rx_busy.eq(0)
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)
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).Elif(rx_bitcount == 9,
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rx_busy.eq(0),
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If(rx, # verify stop bit
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rx_data.eq(rx_reg),
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rx_done.eq(1)
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)
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).Else(
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rx_reg.eq(Cat(rx_reg[1:], rx))
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)
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)
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)
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]
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self.sync += \
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If(rx_busy,
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + tuning_word)
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).Else(
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
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)
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class RS232PHYTX(Module):
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def __init__(self, pads, tuning_word):
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self.sink = Sink([("data", 8)])
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# # #
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uart_clk_txen = Signal()
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phase_accumulator_tx = Signal(32)
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pads.tx.reset = 1
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tx_reg = Signal(8)
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tx_bitcount = Signal(4)
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tx_busy = Signal()
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self.sync += [
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self.sink.ack.eq(0),
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If(self.sink.stb & ~tx_busy & ~self.sink.ack,
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tx_reg.eq(self.sink.data),
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tx_bitcount.eq(0),
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tx_busy.eq(1),
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pads.tx.eq(0)
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).Elif(uart_clk_txen & tx_busy,
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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pads.tx.eq(1)
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).Elif(tx_bitcount == 9,
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pads.tx.eq(1),
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tx_busy.eq(0),
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self.sink.ack.eq(1),
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).Else(
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pads.tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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]
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self.sync += [
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If(tx_busy,
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Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word)
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).Else(
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Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
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)
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]
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class RS232PHY(Module, AutoCSR):
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def __init__(self, pads, clk_freq, baudrate=115200):
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self._tuning_word = CSRStorage(32, reset=int((baudrate/clk_freq)*2**32))
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self.submodules.tx = RS232PHYTX(pads, self._tuning_word.storage)
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self.submodules.rx = RS232PHYRX(pads, self._tuning_word.storage)
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self.sink, self.source = self.tx.sink, self.rx.source
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def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
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if sink_cd != source_cd:
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fifo = AsyncFIFO([("data", 8)], depth)
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return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
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else:
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return SyncFIFO([("data", 8)], depth)
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class UART(Module, AutoCSR):
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def __init__(self, phy,
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tx_fifo_depth=16,
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rx_fifo_depth=16,
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phy_cd="sys"):
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self._rxtx = CSR(8)
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self._txfull = CSRStatus()
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self._rxempty = CSRStatus()
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self.submodules.ev = EventManager()
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self.ev.tx = EventSourceProcess()
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self.ev.rx = EventSourceProcess()
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self.ev.finalize()
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# # #
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# TX
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tx_fifo = _get_uart_fifo(tx_fifo_depth, source_cd=phy_cd)
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self.submodules += tx_fifo
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self.comb += [
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tx_fifo.sink.stb.eq(self._rxtx.re),
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tx_fifo.sink.data.eq(self._rxtx.r),
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self._txfull.status.eq(~tx_fifo.sink.ack),
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Record.connect(tx_fifo.source, phy.sink),
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# Generate TX IRQ when tx_fifo becomes non-full
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self.ev.tx.trigger.eq(~tx_fifo.sink.ack)
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]
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# RX
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rx_fifo = _get_uart_fifo(rx_fifo_depth, sink_cd=phy_cd)
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self.submodules += rx_fifo
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self.comb += [
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Record.connect(phy.source, rx_fifo.sink),
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self._rxempty.status.eq(~rx_fifo.source.stb),
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self._rxtx.w.eq(rx_fifo.source.data),
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rx_fifo.source.ack.eq(self.ev.rx.clear),
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# Generate RX IRQ when tx_fifo becomes non-empty
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self.ev.rx.trigger.eq(~rx_fifo.source.stb)
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]
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