291 lines
7.9 KiB
Python
291 lines
7.9 KiB
Python
import collections
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Operator, _Slice, _Assign, _ArrayProxy
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from migen.fhdl.visit import NodeVisitor, NodeTransformer
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def bitreverse(s):
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length, signed = value_bits_sign(s)
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l = [s[i] for i in reversed(range(length))]
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return Cat(*l)
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def flat_iteration(l):
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for element in l:
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if isinstance(element, collections.Iterable):
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for element2 in flat_iteration(element):
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yield element2
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else:
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yield element
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class _SignalLister(NodeVisitor):
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def __init__(self):
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self.output_list = set()
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def visit_Signal(self, node):
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self.output_list.add(node)
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class _TargetLister(NodeVisitor):
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def __init__(self):
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self.output_list = set()
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self.target_context = False
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def visit_Signal(self, node):
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if self.target_context:
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self.output_list.add(node)
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def visit_Assign(self, node):
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self.target_context = True
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self.visit(node.l)
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self.target_context = False
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def list_signals(node):
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lister = _SignalLister()
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lister.visit(node)
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return lister.output_list
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def list_targets(node):
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lister = _TargetLister()
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lister.visit(node)
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return lister.output_list
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def group_by_targets(sl):
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groups = []
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for statement in flat_iteration(sl):
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targets = list_targets(statement)
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processed = False
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for g in groups:
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if not targets.isdisjoint(g[0]):
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g[0].update(targets)
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g[1].append(statement)
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processed = True
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break
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if not processed:
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groups.append((targets, [statement]))
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return groups
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def list_special_ios(f, ins, outs, inouts):
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r = set()
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for special in f.specials:
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r |= special.list_ios(ins, outs, inouts)
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return r
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class _ClockDomainLister(NodeVisitor):
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def __init__(self):
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self.clock_domains = set()
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def visit_ClockSignal(self, node):
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self.clock_domains.add(node.cd)
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def visit_ResetSignal(self, node):
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self.clock_domains.add(node.cd)
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def visit_clock_domains(self, node):
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for clockname, statements in node.items():
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self.clock_domains.add(clockname)
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self.visit(statements)
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def list_clock_domains_expr(f):
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cdl = _ClockDomainLister()
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cdl.visit(f)
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return cdl.clock_domains
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def list_clock_domains(f):
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r = list_clock_domains_expr(f)
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for special in f.specials:
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r |= special.list_clock_domains()
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for cd in f.clock_domains:
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r.add(cd.name)
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return r
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def is_variable(node):
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if isinstance(node, Signal):
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return node.variable
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elif isinstance(node, _Slice):
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return is_variable(node.value)
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elif isinstance(node, Cat):
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arevars = list(map(is_variable, node.l))
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r = arevars[0]
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for x in arevars:
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if x != r:
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raise TypeError
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return r
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else:
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raise TypeError
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def insert_reset(rst, sl):
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targets = list_targets(sl)
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resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
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return [If(rst, *resetcode).Else(*sl)]
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def value_bits_sign(v):
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if isinstance(v, bool):
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return 1, False
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elif isinstance(v, int):
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return bits_for(v), v < 0
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elif isinstance(v, Signal):
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return v.nbits, v.signed
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elif isinstance(v, (ClockSignal, ResetSignal)):
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return 1, False
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elif isinstance(v, _Operator):
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obs = list(map(value_bits_sign, v.operands))
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if v.op == "+" or v.op == "-":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return max(obs[0][0], obs[1][0]) + 1, False
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return max(obs[0][0], obs[1][0]) + 1, True
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elif not obs[0][1] and obs[1][1]:
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# first operand unsigned (add sign bit), second operand signed
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return max(obs[0][0] + 1, obs[1][0]) + 1, True
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else:
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# first signed, second operand unsigned (add sign bit)
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return max(obs[0][0], obs[1][0] + 1) + 1, True
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elif v.op == "*":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return obs[0][0] + obs[1][0]
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return obs[0][0] + obs[1][0] - 1
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else:
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# one operand signed, the other unsigned (add sign bit)
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return obs[0][0] + obs[1][0] + 1 - 1
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elif v.op == "<<<":
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if obs[1][1]:
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extra = 2**(obs[1][0] - 1) - 1
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else:
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extra = 2**obs[1][0] - 1
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return obs[0][0] + extra, obs[0][1]
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elif v.op == ">>>":
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if obs[1][1]:
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extra = 2**(obs[1][0] - 1)
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else:
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extra = 0
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return obs[0][0] + extra, obs[0][1]
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elif v.op == "&" or v.op == "^" or v.op == "|":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return max(obs[0][0], obs[1][0]), False
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return max(obs[0][0], obs[1][0]), True
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elif not obs[0][1] and obs[1][1]:
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# first operand unsigned (add sign bit), second operand signed
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return max(obs[0][0] + 1, obs[1][0]), True
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else:
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# first signed, second operand unsigned (add sign bit)
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return max(obs[0][0], obs[1][0] + 1), True
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elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
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or v.op == ">" or v.op == ">=":
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return 1, False
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elif v.op == "~":
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return obs[0]
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else:
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raise TypeError
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elif isinstance(v, _Slice):
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return v.stop - v.start, value_bits_sign(v.value)[1]
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elif isinstance(v, Cat):
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return sum(value_bits_sign(sv)[0] for sv in v.l), False
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elif isinstance(v, Replicate):
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return (value_bits_sign(v.v)[0])*v.n, False
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elif isinstance(v, _ArrayProxy):
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bsc = map(value_bits_sign, v.choices)
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return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
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else:
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raise TypeError
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# Basics are FHDL structure elements that back-ends are not required to support
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# but can be expressed in terms of other elements (lowered) before conversion.
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class _BasicLowerer(NodeTransformer):
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def __init__(self, clock_domains):
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self.comb = []
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self.target_context = False
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self.extra_stmts = []
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self.clock_domains = clock_domains
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def visit_Assign(self, node):
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old_target_context, old_extra_stmts = self.target_context, self.extra_stmts
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self.extra_stmts = []
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self.target_context = True
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lhs = self.visit(node.l)
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self.target_context = False
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rhs = self.visit(node.r)
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r = _Assign(lhs, rhs)
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if self.extra_stmts:
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r = [r] + self.extra_stmts
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self.target_context, self.extra_stmts = old_target_context, old_extra_stmts
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return r
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def visit_ArrayProxy(self, node):
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array_muxed = Signal(value_bits_sign(node), variable=True)
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if self.target_context:
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k = self.visit(node.key)
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cases = {}
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for n, choice in enumerate(node.choices):
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cases[n] = [self.visit_Assign(_Assign(choice, array_muxed))]
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self.extra_stmts.append(Case(k, cases).makedefault())
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else:
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cases = dict((n, _Assign(array_muxed, self.visit(choice)))
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for n, choice in enumerate(node.choices))
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self.comb.append(Case(self.visit(node.key), cases).makedefault())
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return array_muxed
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def visit_ClockSignal(self, node):
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return self.clock_domains[node.cd].clk
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def visit_ResetSignal(self, node):
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return self.clock_domains[node.cd].rst
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def lower_basics(f):
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bl = _BasicLowerer(f.clock_domains)
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f = bl.visit(f)
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f.comb += bl.comb
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for special in f.specials:
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for obj, attr, direction in special.iter_expressions():
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if direction != SPECIAL_INOUT:
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# inouts are only supported by Migen when connected directly to top-level
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# in this case, they are Signal and never need lowering
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bl.comb = []
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bl.target_context = direction != SPECIAL_INPUT
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bl.extra_stmts = []
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expr = getattr(obj, attr)
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expr = bl.visit(expr)
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setattr(obj, attr, expr)
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f.comb += bl.comb + bl.extra_stmts
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return f
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class _ClockDomainRenamer(NodeVisitor):
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def __init__(self, old, new):
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self.old = old
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self.new = new
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def visit_ClockSignal(self, node):
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if node.cd == self.old:
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node.cd = self.new
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def visit_ResetSignal(self, node):
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if node.cd == self.old:
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node.cd = self.new
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def rename_clock_domain_expr(f, old, new):
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cdr = _ClockDomainRenamer(old, new)
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cdr.visit(f)
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def rename_clock_domain(f, old, new):
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rename_clock_domain_expr(f, old, new)
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f.sync[new] = f.sync[old]
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del f.sync[old]
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for special in f.specials:
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special.rename_clock_domain(old, new)
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try:
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cd = f.clock_domains[old]
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except KeyError:
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pass
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else:
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cd.rename(new)
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