130 lines
5.3 KiB
Plaintext
130 lines
5.3 KiB
Plaintext
__ ___ _ ____ _____
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/ |/ / (_) / __/__ / ___/
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/ /|_/ / / / _\ \/ _ \/ /__
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/_/ /_/ /_/ /___/\___/\___/
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Copyright 2007-2015 / M-Labs Ltd
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Copyright 2012-2015 / Enjoy-Digital
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a high performance and small footprint SoC based on Migen
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[> Features
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-----------
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* LatticeMico32 CPU, modified to include an optional MMU (experimental).
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* mor1kx (a better OpenRISC implementation) as alternative CPU option.
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* High performance memory controller capable of issuing several SDRAM commands
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per FPGA cycle.
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* Supports SDR, DDR, LPDDR, DDR2 and DDR3.
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* Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI
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flash controller, Ethernet MAC, and more.
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* High performance:
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- on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR
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SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
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- on Kintex-7, 125MHz system clock frequencies (up to 200MHz without DDR3),
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64Gbps DDR3 SDRAM bandwidth.
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* Low resource usage: basic implementation fits easily in Spartan-6 LX9.
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* Portable and easy to customize thanks to Python- and Migen-based
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architecture.
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* Design new peripherals using Migen and benefit from automatic CSR maps
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and logic, etc.
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* Possibility to encapsulate legacy Verilog/VHDL code.
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* Complex FPGA cores that can be used integrated in MiSoC or in standalone:
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- LiteEth: a small footprint and configurable Ethernet core
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- LiteSATA: a small footprint and configurable SATA core
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- LiteScope: a small footprint and configurable logic analyzer core
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MiSoC comes with built-in support for the following boards:
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* Mixxeo, the digital video mixer from M-Labs [XC6SLX45]
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* Milkymist One, the original M-Labs video synthesizer [XC6SLX45]
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* Papilio Pro, a simple and low-cost development board [XC6SLX9]
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* Pipistrello, a simple board with USB and HDMI [XC6SLX45]
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* De0 Nano, a simple and low-cost development board [CYCLONEIV]
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* KC705, a Kintex-7 devboard from Xilinx [XC7K325T]
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MiSoC is portable and support for other boards can easily be added as external
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modules.
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[> Quick start guide
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--------------------
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1. Install Python 3.3+, Migen and FPGA vendor's development tools.
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Get Migen from: https://github.com/m-labs/migen
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2. Install JTAG tools.
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For Mixxeo and M1: http://urjtag.org
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For Papilio Pro and KC705: http://xc3sprog.sourceforge.net
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For De0 Nano: USBBlaster from Altera
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We recommend using xc3sprog for Xilinx devices, but Vivado programmer
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is also supported for Xilinx 7-series.
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3. (Optional, only needed if you want to flash the bistream/software)
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Obtain and build any required flash proxy bitstreams. Flash proxy bitstreams
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give JTAG access to a flash chip through the FPGA.
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For Mixxeo and M1: https://github.com/m-labs/fjmem-m1
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For Papilio Pro: https://github.com/GadgetFactory/Papilio-Loader
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(xc3sprog/trunk/bscan_spi/bscan_spi_lx9_papilio.bit)
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For KC705: https://github.com/m-labs/bscan_spi_kc705
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4. Compile and install binutils. Take the latest version from GNU.
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mkdir build && cd build
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../configure --target=lm32-elf
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make
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make install
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5. Compile and install GCC. Take gcc-core and gcc-g++ from GNU (version 4.5 or >=4.9).
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rm -rf libstdc++-v3
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mkdir build && cd build
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../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc --disable-libssp
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make
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make install
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6. Build and flash the BIOS and bitstream. Run from MiSoC:
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For Mixxeo: ./make.py all
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For M1: ./make.py -p m1 all
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For Papilio Pro: ./make.py -t ppro all
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For Pipistrello: ./make.py -t pipistrello all
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For De0 Nano: ./make.py -t de0nano all load-bitstream
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For KC705: ./make.py -t kc705 all
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If just want to load the bitstream in volatile SRAM use:
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all load-bitstream
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7. Run a terminal program on the board's serial port at 115200 8-N-1.
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You should get the BIOS prompt.
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8. Read and experiment with the source!
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Come to our IRC channel and mailing list!
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A simple target is provided to test MiSoC easily with your board:
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Create your target with a clock and serial pins.
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Build and test it: ./make.py -t simple -p your_platform all load-bitstream
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If you don't have access to a FPGA board, you can also try MiSoC with Verilator:
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Download and install Verilator: http://www.veripool.org/
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Test it: ./make.py -t simple -p sim build-bitstream
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[> License
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----------
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MiSoC is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use MiSoC for
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closed-source proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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* tell us that you are using MiSoC
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* cite MiSoC in publications related to research it has helped
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* send us feedback and suggestions for improvements
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* send us bug reports when something goes wrong
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* send us the modifications and improvements you have done to MiSoC.
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The use of "git format-patch" is recommended. If your submission is large and
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complex and/or you are not sure how to proceed, feel free to discuss it on
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the mailing list or IRC (#m-labs on Freenode) beforehand.
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See LICENSE file for full copyright and license info.
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[> Links
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--------
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Web:
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http://m-labs.hk
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http://enjoy-digital.fr
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Code repository:
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https://github.com/m-labs/misoc
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You can contact us on the public mailing list devel [AT] lists.m-labs.hk.
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