116 lines
3.7 KiB
Python
116 lines
3.7 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.core import LiteEthUDPIPCore
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from misoclib.com.liteeth.core.etherbone import LiteEthEtherbone
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from misoclib.com.liteeth.test.common import *
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from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp, etherbone
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ip_address = 0x12345678
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mac_address = 0x12345678abcd
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False)
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self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False)
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self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False)
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self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
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self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
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self.submodules.sram = wishbone.SRAM(1024)
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.master.bus, self.sram.bus)
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(100):
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yield
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test_probe = True
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test_writes = True
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test_reads = True
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# test probe
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if test_probe:
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packet = etherbone.EtherbonePacket()
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packet.pf = 1
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self.etherbone_model.send(packet)
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yield from self.etherbone_model.receive()
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print("probe: " + str(bool(self.etherbone_model.rx_packet.pr)))
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for i in range(8):
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# test writes
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if test_writes:
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writes_datas = [j for j in range(16)]
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writes = etherbone.EtherboneWrites(base_addr=0x1000, datas=writes_datas)
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record = etherbone.EtherboneRecord()
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record.writes = writes
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record.reads = None
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record.bca = 0
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record.rca = 0
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record.rff = 0
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record.cyc = 0
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record.wca = 0
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record.wff = 0
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record.byte_enable = 0xf
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record.wcount = len(writes_datas)
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record.rcount = 0
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packet = etherbone.EtherbonePacket()
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packet.records = [record]
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self.etherbone_model.send(packet)
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for i in range(256):
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yield
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# test reads
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if test_reads:
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reads_addrs = [0x1000 + 4*j for j in range(16)]
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reads = etherbone.EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
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record = etherbone.EtherboneRecord()
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record.writes = None
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record.reads = reads
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record.bca = 0
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record.rca = 0
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record.rff = 0
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record.cyc = 0
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record.wca = 0
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record.wff = 0
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record.byte_enable = 0xf
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record.wcount = 0
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record.rcount = len(reads_addrs)
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packet = etherbone.EtherbonePacket()
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packet.records = [record]
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self.etherbone_model.send(packet)
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yield from self.etherbone_model.receive()
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loopback_writes_datas = []
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loopback_writes_datas = self.etherbone_model.rx_packet.records.pop().writes.get_datas()
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# check results
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s, l, e = check(writes_datas, loopback_writes_datas)
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True) |