132 lines
4.6 KiB
Python
132 lines
4.6 KiB
Python
from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.frontend.common import *
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class LiteSATAStripingTX(Module):
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"""SATA Striping TX
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Split cmds and writes data on N different controllers.
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This module provides a mirroring_mode that is used by the mirroring module to
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dispatch identicals writes to the controllers. This avoid code duplication in
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between striping and mirroring modules. In this special case, port's data width
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is dw (same as controllers)
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"""
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def __init__(self, n, dw, mirroring_mode=False):
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self.sink = sink = Sink(command_tx_description(dw*n if not mirroring_mode else dw))
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self.sources = sources = [Source(command_tx_description(dw)) for i in range(n)]
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# # #
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split = Signal()
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already_acked = Signal(n)
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self.sync += If(split & sink.stb,
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already_acked.eq(already_acked | Cat(*[s.ack for s in sources])),
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If(sink.ack, already_acked.eq(0))
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)
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(0),
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If(sink.stb & sink.sop,
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NextState("SPLIT")
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).Else(
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sink.ack.eq(1)
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)
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)
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# split data and ctrl signals (except stb & ack managed in fsm)
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for i, s in enumerate(sources):
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self.comb += Record.connect(sink, s, leave_out=set(["stb", "ack", "data"]))
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if mirroring_mode:
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self.comb += s.data.eq(sink.data)
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else:
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self.comb += s.data.eq(sink.data[i*dw:(i+1)*dw])
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fsm.act("SPLIT",
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split.eq(1),
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[s.stb.eq(sink.stb & ~already_acked[i]) for i, s in enumerate(sources)],
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sink.ack.eq(optree("&", [s.ack | already_acked[i] for i, s in enumerate(sources)])),
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If(sink.stb & sink.eop & sink.ack,
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NextState("IDLE")
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)
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)
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class LiteSATAStripingRX(Module):
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"""SATA Striping RX
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Combine acknowledges and reads data from N different controllers.
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This module provides a mirroring_mode that is used by the mirroring module to
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dispatch identicals writes to the controllers. This avoid code duplication in
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between striping and mirroring modules. In this special case, port's data width
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is dw (same as controllers)
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"""
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def __init__(self, n, dw, mirroring_mode=False):
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self.sinks = sinks = [Sink(command_rx_description(dw)) for i in range(n)]
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self.source = source = Source(command_rx_description(dw*n if not mirroring_mode else dw))
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# # #
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sop = Signal()
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self.comb += sop.eq(optree("&", [s.stb & s.sop for s in sinks]))
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(sop,
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NextState("COMBINE")
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)
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)
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# use first sink for ctrl signals (except for stb, ack & failed)
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self.comb += Record.connect(sinks[0], source, leave_out=set(["stb", "ack", "failed", "data"]))
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# combine datas
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if mirroring_mode:
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self.comb += source.data.eq(0) # mirroring only used for writes
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else:
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for i, s in enumerate(sinks):
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self.comb += source.data[i*dw:(i+1)*dw].eq(s.data)
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fsm.act("COMBINE",
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source.failed.eq(optree("|", [s.failed for s in sinks])), # XXX verify this is enough
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source.stb.eq(optree("&", [s.stb for s in sinks])),
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[s.ack.eq(source.stb & source.ack) for s in sinks],
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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class LiteSATAStriping(Module):
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"""SATA Striping
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Segment data so that data is stored on N different controllers.
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+----> controller0 (dw)
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port (N*dw) <----+----> controllerX (dw)
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+----> controllerN (dw)
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Characteristics:
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- port's visible capacity = N x controller's visible capacity
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- port's throughput = N x (slowest) controller's throughput
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Can be used to increase capacity and writes/reads throughput.
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"""
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def __init__(self, controllers):
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# # #
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n = len(controllers)
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dw = flen(controllers[0].sink.data)
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self.submodules.tx = LiteSATAStripingTX(n, dw)
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self.submodules.rx = LiteSATAStripingRX(n, dw)
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for i in range(n):
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self.comb += [
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Record.connect(self.tx.sources[i], controllers[i].sink),
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Record.connect(controllers[i].source, self.rx.sinks[i])
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]
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self.sink, self.source = self.tx.sink, self.rx.source
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