litex/migen
Sebastien Bourdeauducq 6aa1e0c199 actorlib/spi/DMAWriteController: len -> flen 2013-07-11 19:22:56 +02:00
..
actorlib actorlib/spi/DMAWriteController: len -> flen 2013-07-11 19:22:56 +02:00
bank New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
bus dfi: split phase description 2013-07-10 19:56:47 +02:00
fhdl fhdl: mark variable as deprecated 2013-06-30 20:14:20 +02:00
flow New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
genlib genlib/misc: remove bitreverse 2013-06-30 14:31:25 +02:00
pytholite pytholite: fix kwargs handling 2013-07-03 17:20:05 +02:00
sim New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00