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30 lines
1.4 KiB
Python
30 lines
1.4 KiB
Python
####################################################################################################
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# DISCLAIMER: Provides retro-compatibility layer for add_spi_flash with previous LiteX core.
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# Will soon no longer work, please don't use in new designs.
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####################################################################################################
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from math import ceil
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from litex.soc.integration.soc import SoCRegion
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def add_spi_flash(soc, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None):
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# Imports.
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from litex.soc.cores.spi_flash import SpiFlash
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# Checks.
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assert dummy_cycles is not None # FIXME: Get dummy_cycles from SPI Flash
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assert mode in ["1x", "4x"]
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if clk_freq is None: clk_freq = soc.clk_freq/2 # FIXME: Get max clk_freq from SPI Flash
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# Core.
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soc.check_if_exists(name)
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spiflash = SpiFlash(
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pads = soc.platform.request(name if mode == "1x" else name + mode),
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dummy = dummy_cycles,
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div = ceil(soc.clk_freq/clk_freq),
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with_bitbang = True,
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endianness = soc.cpu.endianness)
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spiflash.add_clk_primitive(soc.platform.device)
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setattr(soc.submodules, name, spiflash)
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spiflash_region = SoCRegion(origin=soc.mem_map.get(name, None), size=0x1000000) # FIXME: Get size from SPI Flash
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soc.bus.add_slave(name=name, slave=spiflash.bus, region=spiflash_region)
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