24 lines
481 B
Python
24 lines
481 B
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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d = 100
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d_b = bits_for(d-1)
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w = 32
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a1 = Signal(BV(d_b))
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d1 = Signal(BV(w))
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we1 = Signal(BV(4))
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dw1 = Signal(BV(w))
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re = Signal()
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p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
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a2 = Signal(BV(d_b))
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d2 = Signal(BV(w))
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re2 = Signal()
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p2 = MemoryPort(a2, d2, re=re2)
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mem = Memory(w, d, p1, p2, init=[5, 18, 32])
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f = Fragment(memories=[mem])
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v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2, re2})
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print(v)
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