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140 lines
4 KiB
Python
140 lines
4 KiB
Python
from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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class LiteEthIPV4Depacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_mac_description(8),
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eth_ipv4_description(8),
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ipv4_header,
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ipv4_header_len)
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class LiteEthIPV4Packetizer(LiteEthPacketizer):
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def __init__(self):
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LiteEthPacketizer.__init__(self,
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eth_ipv4_description(8),
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eth_mac_description(8),
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ipv4_header,
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ipv4_header_len)
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class LiteEthIPTX(Module):
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def __init__(self, mac_address, ip_address, arp_table):
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self.sink = Sink(eth_ipv4_user_description(8))
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self.source = Source(eth_mac_description(8))
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###
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packetizer = LiteEthIPV4Packetizer()
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self.submodules += packetizer
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self.comb += [
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Record.connect(self.sink, packetizer.sink),
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packetizer.sink.version.eq(0x5),
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packetizer.sink.ihl.eq(0x4),
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packetizer.sink.dscp.eq(0),
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packetizer.sink.ecn.eq(0),
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packetizer.sink.identification.eq(0),
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packetizer.sink.flags.eq(0),
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packetizer.sink.fragment_offset.eq(0),
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packetizer.sink.time_to_live.eq(0x80),
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packetizer.sink.source_ip_address.eq(ip_address),
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packetizer.sink.options.eq(0)
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]
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sink = packetizer.source
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destination_mac_address = Signal(48)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("SEND_MAC_ADDRESS_REQUEST")
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)
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)
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fsm.act("SEND_MAC_ADDRESS_REQUEST",
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arp_table.request.stb.eq(1),
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arp_table.request.ip_address.eq(self.sink.destination_ip_address),
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If(arp_table.request.stb & arp_table.request.ack,
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NextState("WAIT_MAC_ADDRESS_RESPONSE")
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)
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)
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fsm.act("WAIT_MAC_ADDRESS_RESPONSE",
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# XXX add timeout
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If(arp_table.response.stb,
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arp_table.response.ack.eq(1),
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# XXX manage failed
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NextState("SEND")
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)
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)
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self.sync += If(arp_table.response.stb, destination_mac_address.eq(arp_table.response.mac_address))
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fsm.act("SEND",
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Record.connect(packetizer.source, self.source),
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self.source.ethernet_type.eq(ethernet_type_ip),
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self.source.destination_mac_address.eq(destination_mac_address),
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self.source.source_mac_address.eq(mac_address),
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# XXX compute check sum
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If(self.source.stb & self.source.eop & self.source.ack,
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# XXX manage failed
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NextState("IDLE")
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)
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)
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class LiteEthIPRX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = Sink(eth_mac_description(8))
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self.source = source = Source(eth_ipv4_user_description(8))
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###
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depacketizer = LiteEthIPV4Depacketizer()
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self.submodules += depacketizer
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self.comb += Record.connect(self.sink, depacketizer.sink)
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sink = depacketizer.source
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal()
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self.comb += valid.eq(1) # XXX FIXME
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fsm.act("CHECK",
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If(valid,
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NextState("PRESENT")
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).Else(
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NextState("DROP")
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)
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),
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fsm.act("PRESENT",
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source.stb.eq(sink.stb),
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source.sop.eq(sink.sop),
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source.eop.eq(sink.eop),
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sink.ack.eq(source.ack),
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source.total_length.eq(sink.total_length),
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source.protocol.eq(sink.protocol),
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source.destination_ip_address.eq(sink.destination_ip_address),
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source.data.eq(sink.data),
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source.error.eq(sink.error),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("DROP",
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sink.ack.eq(1),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthIP(Module):
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def __init__(self, mac, mac_address, ip_address, arp_table):
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self.submodules.tx = LiteEthIPTX(mac_address, ip_address, arp_table)
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self.submodules.rx = LiteEthIPRX(mac_address, ip_address)
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mac_port = mac.crossbar.get_port(ethernet_type_ip)
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self.comb += [
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Record.connect(self.tx.source, mac_port.sink),
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Record.connect(mac_port.source, self.rx.sink)
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]
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self.sink, self.source = self.tx.sink, self.rx.source
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