274 lines
7.2 KiB
Python
274 lines
7.2 KiB
Python
from migen.fhdl.std import *
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from migen.bus.asmibus import *
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from migen.genlib.roundrobin import *
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from migen.genlib.fsm import FSM
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from migen.genlib.misc import optree
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from milkymist.asmicon.multiplexer import *
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# Row:Bank:Col address mapping
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class _AddressSlicer:
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def __init__(self, geom_settings, address_align):
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self.geom_settings = geom_settings
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self.address_align = address_align
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self._b1 = self.geom_settings.col_a - self.address_align
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self._b2 = self._b1 + self.geom_settings.bank_a
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def row(self, address):
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if isinstance(address, int):
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return address >> self._b2
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else:
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return address[self._b2:]
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def bank(self, address):
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if isinstance(address, int):
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return (address & (2**self._b2 - 1)) >> self._b1
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else:
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return address[self._b1:self._b2]
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def col(self, address):
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if isinstance(address, int):
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return (address & (2**self._b1 - 1)) << self.address_align
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else:
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return Cat(Replicate(0, self.address_align), address[:self._b1])
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class _Selector(Module):
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def __init__(self, slicer, bankn, slots):
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nslots = len(slots)
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self.stb = Signal()
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self.ack = Signal()
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self.tag = Signal(max=nslots)
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self.adr = Signal(slots[0].adr.nbits)
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self.we = Signal()
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# derived classes should drive rr.request
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self.submodules.rr = RoundRobin(nslots, SP_CE)
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###
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# Multiplex
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rr = self.rr
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state = Signal(2)
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self.comb += [
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state.eq(Array(slot.state for slot in slots)[rr.grant]),
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self.adr.eq(Array(slot.adr for slot in slots)[rr.grant]),
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self.we.eq(Array(slot.we for slot in slots)[rr.grant]),
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self.stb.eq(
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(slicer.bank(self.adr) == bankn) \
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& (state == SLOT_PENDING)),
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rr.ce.eq(self.ack | ~self.stb),
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self.tag.eq(rr.grant)
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]
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self.comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
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for i, slot in enumerate(slots)]
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self.complete_selector(slicer, bankn, slots)
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class _SimpleSelector(_Selector):
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def complete_selector(self, slicer, bankn, slots):
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for i, slot in enumerate(slots):
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self.comb += self.rr.request[i].eq(
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(slicer.bank(slot.adr) == bankn) & \
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(slot.state == SLOT_PENDING))
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class _FullSelector(_Selector):
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def complete_selector(self, slicer, bankn, slots):
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rr = self.rr
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# List outstanding requests for our bank
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outstandings = []
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for slot in slots:
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outstanding = Signal()
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self.comb += outstanding.eq(
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(slicer.bank(slot.adr) == bankn) & \
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(slot.state == SLOT_PENDING))
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outstandings.append(outstanding)
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# Row tracking
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openrow_r = Signal(slicer.geom_settings.row_a)
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openrow_n = Signal(slicer.geom_settings.row_a)
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openrow = Signal(slicer.geom_settings.row_a)
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self.comb += [
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openrow_n.eq(slicer.row(self.adr)),
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If(self.stb,
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openrow.eq(openrow_n)
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).Else(
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openrow.eq(openrow_r)
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)
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]
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self.sync += If(self.stb & self.ack, openrow_r.eq(openrow_n))
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hits = []
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for slot, os in zip(slots, outstandings):
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hit = Signal()
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self.comb += hit.eq((slicer.row(slot.adr) == openrow) & os)
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hits.append(hit)
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# Determine best request
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rr = RoundRobin(self.nslots, SP_CE)
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has_hit = Signal()
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self.comb += has_hit.eq(optree("|", hits))
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best_hit = [rr.request[i].eq(hit)
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for i, hit in enumerate(hits)]
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best_fallback = [rr.request[i].eq(os)
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for i, os in enumerate(outstandings)]
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select_stmt = If(has_hit,
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*best_hit
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).Else(
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*best_fallback
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)
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if slots[0].time:
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# Implement anti-starvation timer
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matures = []
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for slot, os in zip(slots, outstandings):
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mature = Signal()
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comb.append(mature.eq(slot.mature & os))
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matures.append(mature)
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has_mature = Signal()
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self.comb += has_mature.eq(optree("|", matures))
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best_mature = [rr.request[i].eq(mature)
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for i, mature in enumerate(matures)]
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select_stmt = If(has_mature, *best_mature).Else(select_stmt)
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self.comb += select_stmt
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class _Buffer(Module):
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def __init__(self, source):
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self.stb = Signal()
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self.ack = Signal()
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self.tag = Signal(source.tag.bv)
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self.adr = Signal(source.adr.bv)
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self.we = Signal()
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###
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en = Signal()
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self.comb += [
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en.eq(self.ack | ~self.stb),
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source.ack.eq(en)
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]
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self.sync += [
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If(en,
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self.stb.eq(source.stb),
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self.tag.eq(source.tag),
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self.adr.eq(source.adr),
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self.we.eq(source.we)
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)
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]
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class BankMachine(Module):
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def __init__(self, geom_settings, timing_settings, address_align, bankn, slots, full_selector):
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self.refresh_req = Signal()
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self.refresh_gnt = Signal()
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self.cmd = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a,
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bits_for(len(slots)-1))
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###
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# Sub components
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slicer = _AddressSlicer(geom_settings, address_align)
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if full_selector:
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selector = _FullSelector(slicer, bankn, slots)
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self.submodules.buf = _Buffer(selector)
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cmdsource = self.buf
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else:
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selector = _SimpleSelector(slicer, bankn, slots)
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cmdsource = selector
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self.submodules += selector
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# Row tracking
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has_openrow = Signal()
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openrow = Signal(geom_settings.row_a)
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hit = Signal()
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self.comb += hit.eq(openrow == slicer.row(cmdsource.adr))
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track_open = Signal()
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track_close = Signal()
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self.sync += [
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If(track_open,
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has_openrow.eq(1),
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openrow.eq(slicer.row(cmdsource.adr))
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),
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If(track_close,
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has_openrow.eq(0)
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)
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]
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# Address generation
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s_row_adr = Signal()
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self.comb += [
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self.cmd.ba.eq(bankn),
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If(s_row_adr,
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self.cmd.a.eq(slicer.row(cmdsource.adr))
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).Else(
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self.cmd.a.eq(slicer.col(cmdsource.adr))
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)
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]
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self.comb += self.cmd.tag.eq(cmdsource.tag)
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# Respect write-to-precharge specification
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precharge_ok = Signal()
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t_unsafe_precharge = 2 + timing_settings.tWR - 1
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unsafe_precharge_count = Signal(max=t_unsafe_precharge+1)
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self.comb += precharge_ok.eq(unsafe_precharge_count == 0)
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self.sync += [
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If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,
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unsafe_precharge_count.eq(t_unsafe_precharge)
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).Elif(~precharge_ok,
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unsafe_precharge_count.eq(unsafe_precharge_count-1)
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)
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]
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# Control and command generation FSM
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fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[
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("TRP", "ACTIVATE", timing_settings.tRP-1),
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("TRCD", "REGULAR", timing_settings.tRCD-1)
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])
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self.submodules += fsm
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fsm.act(fsm.REGULAR,
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If(self.refresh_req,
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fsm.next_state(fsm.REFRESH)
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).Elif(cmdsource.stb,
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If(has_openrow,
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If(hit,
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# NB: write-to-read specification is enforced by multiplexer
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self.cmd.stb.eq(1),
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cmdsource.ack.eq(self.cmd.ack),
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self.cmd.is_read.eq(~cmdsource.we),
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self.cmd.is_write.eq(cmdsource.we),
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self.cmd.cas_n.eq(0),
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self.cmd.we_n.eq(~cmdsource.we)
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).Else(
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fsm.next_state(fsm.PRECHARGE)
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)
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).Else(
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fsm.next_state(fsm.ACTIVATE)
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)
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)
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)
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fsm.act(fsm.PRECHARGE,
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# Notes:
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# 1. we are presenting the column address, A10 is always low
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# 2. since we always go to the ACTIVATE state, we do not need
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# to assert track_close.
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If(precharge_ok,
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self.cmd.stb.eq(1),
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If(self.cmd.ack, fsm.next_state(fsm.TRP)),
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self.cmd.ras_n.eq(0),
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self.cmd.we_n.eq(0)
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)
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)
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fsm.act(fsm.ACTIVATE,
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s_row_adr.eq(1),
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track_open.eq(1),
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self.cmd.stb.eq(1),
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If(self.cmd.ack, fsm.next_state(fsm.TRCD)),
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self.cmd.ras_n.eq(0)
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)
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fsm.act(fsm.REFRESH,
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self.refresh_gnt.eq(precharge_ok),
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track_close.eq(1),
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If(~self.refresh_req, fsm.next_state(fsm.REGULAR))
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)
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