139 lines
3.0 KiB
Python
139 lines
3.0 KiB
Python
from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.fhdl.specials import Memory
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFO
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from migen.genlib.fsm import FSM, NextState
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from miscope.std import *
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class RunLengthEncoder(Module, AutoCSR):
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def __init__(self, width, length):
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self.width = width
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self.length = length
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self.sink = rec_dat(width)
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self.source = rec_dat(width)
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self._r_enable = CSRStorage()
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###
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enable = self._r_enable.storage
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stb_i = self.sink.stb
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dat_i = self.sink.dat
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ack_i = self.sink.ack
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# Register Input
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stb_i_d = Signal()
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dat_i_d = Signal(width)
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self.sync += [
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If(stb_i,
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dat_i_d.eq(dat_i),
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stb_i_d.eq(stb_i)
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)
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]
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# Detect change
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change = Signal()
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self.comb += [change.eq(stb_i & (~enable | (dat_i_d != dat_i)))]
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change_d = Signal()
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change_rising = Signal()
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self.sync += If(stb_i, change_d.eq(change))
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self.comb += change_rising.eq(stb_i & (change & ~change_d))
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# Generate RLE word
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rle_cnt = Signal(max=length)
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rle_max = Signal()
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self.comb +=[If(rle_cnt == length, rle_max.eq(enable))]
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self.sync +=[
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If(change | rle_max,
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rle_cnt.eq(0)
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).Else(
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rle_cnt.eq(rle_cnt + 1)
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)
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]
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# Mux RLE word and data
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stb_o = self.source.stb
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dat_o = self.source.dat
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ack_o = self.source.ack
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self.comb +=[
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If(change_rising & ~rle_max,
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stb_o.eq(1),
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dat_o[width-1].eq(1),
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dat_o[:flen(rle_cnt)].eq(rle_cnt)
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).Elif(change_d | rle_max,
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stb_o.eq(stb_i_d),
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dat_o.eq(dat_i_d)
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).Else(
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stb_o.eq(0),
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),
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ack_i.eq(1) #FIXME
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]
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class Recorder(Module, AutoCSR):
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def __init__(self, width, depth):
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self.width = width
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self.trig_sink = rec_hit()
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self.dat_sink = rec_dat(width)
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self._r_trigger = CSR()
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self._r_length = CSRStorage(bits_for(depth))
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self._r_offset = CSRStorage(bits_for(depth))
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self._r_done = CSRStatus()
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self._r_read_en = CSR()
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self._r_read_empty = CSRStatus()
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self._r_read_dat = CSRStatus(width)
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###
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fifo = SyncFIFO(width, depth)
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self.submodules += fifo
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.comb += [
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self._r_read_empty.status.eq(~fifo.readable),
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self._r_read_dat.status.eq(fifo.dout),
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]
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fsm.act("IDLE",
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If(self._r_trigger.re & self._r_trigger.r,
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NextState("PRE_HIT_RECORDING"),
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fifo.flush.eq(1),
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),
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fifo.re.eq(self._r_read_en.re & self._r_read_en.r),
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self._r_done.status.eq(1)
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)
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fsm.act("PRE_HIT_RECORDING",
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fifo.we.eq(self.dat_sink.stb),
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fifo.din.eq(self.dat_sink.dat),
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self.dat_sink.ack.eq(fifo.writable),
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fifo.re.eq(fifo.level >= self._r_offset.storage),
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If(self.trig_sink.stb & self.trig_sink.hit, NextState("POST_HIT_RECORDING"))
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)
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fsm.act("POST_HIT_RECORDING",
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fifo.we.eq(self.dat_sink.stb),
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fifo.din.eq(self.dat_sink.dat),
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self.dat_sink.ack.eq(fifo.writable),
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If(~fifo.writable | (fifo.level >= self._r_length.storage), NextState("IDLE"))
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)
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