Sebastien Bourdeauducq 14ed5c1acc genlib/record: support abstract signal width		2013-07-27 22:18:06 +02:00
..
__init__.py	corelogic -> genlib	2013-02-22 23:19:37 +01:00
cdc.py	genlib: remove direct uses of Fragment	2013-07-24 19:25:14 +02:00
coding.py	coding.py: rewrite If() to make verilog more readable	2013-06-30 11:39:47 +02:00
complex.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
cordic.py	genlib/cordic: cleanup	2013-06-26 22:46:04 +02:00
divider.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
fifo.py	fhdl: RenameClockDomains decorator	2013-07-26 15:42:14 +02:00
fsm.py	fsm.py: set reset_state	2013-07-22 10:30:40 +02:00
ioo.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
misc.py	genlib/misc: remove bitreverse	2013-06-30 14:31:25 +02:00
record.py	genlib/record: support abstract signal width	2013-07-27 22:18:06 +02:00
rob.py	genlib: remove direct uses of Fragment	2013-07-24 19:25:14 +02:00
roundrobin.py	genlib/roundrobin: fix n==1 case (correctly)	2013-07-26 09:33:33 +02:00