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from migen.fhdl.std import *
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from migen.fhdl import verilog
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class Example(Module):
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def __init__(self, n=6):
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self.pad = Signal(n)
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self.t = TSTriple(n)
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self.specials += self.t.get_tristate(self.pad)
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e = Example()
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print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
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