Sebastien Bourdeauducq 50ed73c937 New specification for width and signedness		2012-11-29 21:22:38 +01:00
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abstract_transactions.py	bus/asmibus: swap port position to be consistent with wishbone API	2012-11-17 19:42:39 +01:00
basic1.py	New specification for width and signedness	2012-11-29 21:22:38 +01:00
basic2.py	New specification for width and signedness	2012-11-29 21:22:38 +01:00
dataflow.py	New specification for width and signedness	2012-11-29 21:22:38 +01:00
fir.py	New specification for width and signedness	2012-11-29 21:22:38 +01:00
memory.py	examples/sim/memory: do not use MemoryPort	2012-11-26 18:19:10 +01:00