60 lines
1.3 KiB
Python
60 lines
1.3 KiB
Python
import subprocess
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.core.link.crc import *
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from misoclib.mem.litesata.test.common import *
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class TB(Module):
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def __init__(self, length, random):
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self.submodules.crc = LiteSATACRC()
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self.length = length
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self.random = random
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def get_c_crc(self, datas):
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stdin = ""
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for data in datas:
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stdin += "0x%08x " %data
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stdin += "exit"
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with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
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process.stdin.write(stdin.encode("ASCII"))
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out, err = process.communicate()
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return int(out.decode("ASCII"), 16)
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def gen_simulation(self, selfp):
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# init CRC
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selfp.crc.d = 0
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selfp.crc.ce = 1
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selfp.crc.reset = 1
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yield
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selfp.crc.reset = 0
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# feed CRC with datas
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datas = []
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for i in range(self.length):
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data = seed_to_data(i, self.random)
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datas.append(data)
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selfp.crc.d = data
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yield
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# log results
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yield
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sim_crc = selfp.crc.value
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# stop
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selfp.crc.ce = 0
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for i in range(32):
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yield
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# get C core reference
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c_crc = self.get_c_crc(datas)
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# check results
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s, l, e = check(c_crc, sim_crc)
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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from migen.sim.generic import run_simulation
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length = 8192
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run_simulation(TB(length, True), ncycles=length+100, vcd_name="my.vcd")
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