512 lines
13 KiB
Python
512 lines
13 KiB
Python
import subprocess
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import math
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.test.common import *
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def print_with_prefix(s, prefix=""):
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if not isinstance(s, str):
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s = s.__repr__()
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s = s.split("\n")
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for l in s:
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print(prefix + l)
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# PHY Layer model
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class PHYDword:
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def __init__(self, dat=0):
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self.dat = dat
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self.start = 1
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self.done = 0
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class PHYSource(Module):
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def __init__(self):
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self.source = Source(phy_description(32))
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###
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self.dword = PHYDword()
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def send(self, dword):
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self.dword = dword
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def do_simulation(self, selfp):
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selfp.source.stb = 1
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selfp.source.charisk = 0b0000
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for k, v in primitives.items():
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if v == self.dword.dat:
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selfp.source.charisk = 0b0001
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selfp.source.data = self.dword.dat
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class PHYSink(Module):
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def __init__(self):
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self.sink = Sink(phy_description(32))
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###
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self.dword = PHYDword()
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def receive(self):
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self.dword.done = 0
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while self.dword.done == 0:
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yield
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def do_simulation(self, selfp):
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self.dword.done = 0
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selfp.sink.ack = 1
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if selfp.sink.stb == 1:
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self.dword.done = 1
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self.dword.dat = selfp.sink.data
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class PHYLayer(Module):
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def __init__(self):
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self.submodules.rx = PHYSink()
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self.submodules.tx = PHYSource()
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self.source = self.tx.source
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self.sink = self.rx.sink
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def send(self, dword):
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packet = PHYDword(dword)
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self.tx.send(packet)
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def receive(self):
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yield from self.rx.receive()
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def __repr__(self):
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receiving = "%08x " %self.rx.dword.dat
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receiving += decode_primitive(self.rx.dword.dat)
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receiving += " "*(16-len(receiving))
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sending = "%08x " %self.tx.dword.dat
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sending += decode_primitive(self.tx.dword.dat)
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sending += " "*(16-len(sending))
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return receiving + sending
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# Link Layer model
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def print_link(s):
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print_with_prefix(s, "[LNK]: ")
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def import_scrambler_datas():
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with subprocess.Popen(["./scrambler"], stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
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process.stdin.write("0x10000".encode("ASCII"))
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out, err = process.communicate()
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return [int(e, 16) for e in out.decode("utf-8").split("\n")[:-1]]
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class LinkPacket(list):
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def __init__(self, init=[]):
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self.ongoing = False
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self.done = False
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self.scrambled_datas = import_scrambler_datas()
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for dword in init:
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self.append(dword)
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class LinkRXPacket(LinkPacket):
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def descramble(self):
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for i in range(len(self)):
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self[i] = self[i] ^ self.scrambled_datas[i]
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def check_crc(self):
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stdin = ""
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for v in self[:-1]:
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stdin += "0x%08x " %v
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stdin += "exit"
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with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
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process.stdin.write(stdin.encode("ASCII"))
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out, err = process.communicate()
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crc = int(out.decode("ASCII"), 16)
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r = (self[-1] == crc)
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self.pop()
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return r
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def decode(self):
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self.descramble()
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return self.check_crc()
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class LinkTXPacket(LinkPacket):
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def insert_crc(self):
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stdin = ""
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for v in self:
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stdin += "0x%08x " %v
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stdin += "exit"
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with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
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process.stdin.write(stdin.encode("ASCII"))
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out, err = process.communicate()
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crc = int(out.decode("ASCII"), 16)
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self.append(crc)
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def scramble(self):
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for i in range(len(self)):
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self[i] = self[i] ^ self.scrambled_datas[i]
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def encode(self):
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self.insert_crc()
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self.scramble()
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class LinkLayer(Module):
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def __init__(self, phy, debug=False, random_level=0):
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self.phy = phy
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self.debug = debug
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self.random_level = random_level
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self.tx_packets = []
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self.tx_packet = LinkTXPacket()
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self.rx_packet = LinkRXPacket()
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self.rx_cont = False
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self.rx_last = 0
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self.tx_cont = False
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self.tx_cont_nb = -1
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self.tx_lasts = [0, 0, 0]
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self.scrambled_datas = import_scrambler_datas()
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self.transport_callback = None
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self.send_state = ""
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self.send_states = ["RDY", "SOF", "DATA", "EOF", "WTRM"]
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def set_transport_callback(self, callback):
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self.transport_callback = callback
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def send(self, dword):
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if self.send_state == "RDY":
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self.phy.send(primitives["X_RDY"])
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if dword == primitives["R_RDY"]:
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self.send_state = "SOF"
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elif self.send_state == "SOF":
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self.phy.send(primitives["SOF"])
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self.send_state = "DATA"
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elif self.send_state == "DATA":
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if dword == primitives["HOLD"]:
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self.phy.send(primitives["HOLDA"])
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else:
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self.phy.send(self.tx_packet.pop(0))
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if len(self.tx_packet) == 0:
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self.send_state = "EOF"
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elif self.send_state == "EOF":
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self.phy.send(primitives["EOF"])
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self.send_state = "WTRM"
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elif self.send_state == "WTRM":
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self.phy.send(primitives["WTRM"])
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if dword == primitives["R_OK"]:
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self.tx_packet.done = True
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elif dword == primitives["R_ERR"]:
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self.tx_packet.done = True
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if self.tx_packet.done:
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self.phy.send(primitives["SYNC"])
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def insert_cont(self):
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self.tx_lasts.pop(0)
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self.tx_lasts.append(self.phy.tx.dword.dat)
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self.tx_cont = True
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for i in range(3):
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if not is_primitive(self.tx_lasts[i]):
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self.tx_cont = False
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if self.tx_lasts[i] != self.tx_lasts[0]:
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self.tx_cont = False
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if self.tx_cont:
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if self.tx_cont_nb == 0:
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self.phy.send(primitives["CONT"])
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else:
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self.phy.send(self.scrambled_datas[self.tx_cont_nb])
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self.tx_cont_nb += 1
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else:
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self.tx_cont_nb = 0
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def remove_cont(self, dword):
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if dword == primitives["HOLD"]:
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if self.rx_cont:
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self.tx_lasts = [0, 0, 0]
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if dword == primitives["CONT"]:
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self.rx_cont = True
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elif is_primitive(dword):
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self.rx_last = dword
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self.rx_cont = False
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if self.rx_cont:
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dword = self.rx_last
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return dword
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def callback(self, dword):
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if dword == primitives["X_RDY"]:
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self.phy.send(primitives["R_RDY"])
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elif dword == primitives["WTRM"]:
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self.phy.send(primitives["R_OK"])
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if self.rx_packet.ongoing:
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self.rx_packet.decode()
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if self.transport_callback is not None:
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self.transport_callback(self.rx_packet)
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self.rx_packet.ongoing = False
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elif dword == primitives["HOLD"]:
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self.phy.send(primitives["HOLDA"])
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elif dword == primitives["EOF"]:
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pass
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elif self.rx_packet.ongoing:
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if dword != primitives["HOLD"]:
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n = randn(100)
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if n < self.random_level:
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self.phy.send(primitives["HOLD"])
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else:
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self.phy.send(primitives["R_IP"])
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if not is_primitive(dword):
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self.rx_packet.append(dword)
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elif dword == primitives["SOF"]:
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self.rx_packet = LinkRXPacket()
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self.rx_packet.ongoing = True
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def gen_simulation(self, selfp):
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self.tx_packet.done = True
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self.phy.send(primitives["SYNC"])
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while True:
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yield from self.phy.receive()
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if self.debug:
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print_link(self.phy)
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self.phy.send(primitives["SYNC"])
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rx_dword = self.phy.rx.dword.dat
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rx_dword = self.remove_cont(rx_dword)
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if len(self.tx_packets) != 0:
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if self.tx_packet.done:
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self.tx_packet = self.tx_packets.pop(0)
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self.tx_packet.encode()
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self.send_state = "RDY"
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if not self.tx_packet.done:
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self.send(rx_dword)
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else:
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self.callback(rx_dword)
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self.insert_cont()
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# Transport Layer model
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def print_transport(s):
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print_with_prefix(s, "[TRN]: ")
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def get_field_data(field, packet):
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return (packet[field.dword] >> field.offset) & (2**field.width-1)
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class FIS:
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def __init__(self, packet, description, direction="H2D"):
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self.packet = packet
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self.description = description
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self.direction = direction
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self.decode()
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def decode(self):
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for k, v in self.description.items():
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setattr(self, k, get_field_data(v, self.packet))
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def encode(self):
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for k, v in self.description.items():
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self.packet[v.dword] |= (getattr(self, k) << v.offset)
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def __repr__(self):
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if self.direction == "H2D":
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r = ">>>>>>>>\n"
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else:
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r = "<<<<<<<<\n"
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for k in sorted(self.description.keys()):
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r += k + " : 0x%x" %getattr(self,k) + "\n"
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return r
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class FIS_REG_H2D(FIS):
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def __init__(self, packet=[0]*fis_reg_h2d_cmd_len):
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FIS.__init__(self, packet, fis_reg_h2d_layout)
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self.type = fis_types["REG_H2D"]
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self.direction = "H2D"
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def __repr__(self):
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r = "FIS_REG_H2D\n"
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r += FIS.__repr__(self)
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return r
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class FIS_REG_D2H(FIS):
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def __init__(self, packet=[0]*fis_reg_d2h_cmd_len):
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FIS.__init__(self, packet, fis_reg_d2h_layout)
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self.type = fis_types["REG_D2H"]
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self.direction = "D2H"
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def __repr__(self):
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r = "FIS_REG_D2H\n"
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r += FIS.__repr__(self)
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return r
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class FIS_DMA_ACTIVATE_D2H(FIS):
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def __init__(self, packet=[0]*fis_dma_activate_d2h_cmd_len):
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FIS.__init__(self, packet, fis_dma_activate_d2h_layout)
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self.type = fis_types["DMA_ACTIVATE_D2H"]
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self.direction = "D2H"
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def __repr__(self):
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r = "FIS_DMA_ACTIVATE_D2H\n"
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r += FIS.__repr__(self)
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return r
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class FIS_DATA(FIS):
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def __init__(self, packet=[0], direction="H2D"):
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FIS.__init__(self, packet, fis_data_layout, direction)
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self.type = fis_types["DATA"]
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def __repr__(self):
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r = "FIS_DATA\n"
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r += FIS.__repr__(self)
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for data in self.packet[1:]:
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r += "%08x\n" %data
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return r
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class FIS_UNKNOWN(FIS):
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def __init__(self, packet=[0], direction="H2D"):
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FIS.__init__(self, packet, {}, direction)
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def __repr__(self):
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r = "UNKNOWN\n"
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if self.direction == "H2D":
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r += ">>>>>>>>\n"
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else:
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r += "<<<<<<<<\n"
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for dword in self.packet:
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r += "%08x\n" %dword
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return r
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class TransportLayer(Module):
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def __init__(self, link, debug=False, loopback=False):
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self.link = link
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self.debug = debug
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self.loopback = loopback
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self.link.set_transport_callback(self.callback)
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def set_command_callback(self, callback):
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self.command_callback = callback
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def send(self, fis):
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fis.encode()
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packet = LinkTXPacket(fis.packet)
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self.link.tx_packets.append(packet)
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if self.debug and not self.loopback:
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print_transport(fis)
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def callback(self, packet):
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fis_type = packet[0] & 0xff
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if fis_type == fis_types["REG_H2D"]:
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fis = FIS_REG_H2D(packet)
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elif fis_type == fis_types["REG_D2H"]:
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fis = FIS_REG_D2H(packet)
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elif fis_type == fis_types["DMA_ACTIVATE_D2H"]:
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fis = FIS_DMA_ACTIVATE_D2H(packet)
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elif fis_type == fis_types["DATA"]:
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fis = FIS_DATA(packet, direction="H2D")
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else:
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fis = FIS_UNKNOWN(packet, direction="H2D")
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if self.debug:
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print_transport(fis)
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if self.loopback:
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self.send(fis)
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else:
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self.command_callback(fis)
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# Command Layer model
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class CommandLayer(Module):
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def __init__(self, transport):
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self.transport = transport
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self.transport.set_command_callback(self.callback)
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self.hdd = None
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def set_hdd(self, hdd):
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self.hdd = hdd
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def callback(self, fis):
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resp = None
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if isinstance(fis, FIS_REG_H2D):
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if fis.command == regs["WRITE_DMA_EXT"]:
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resp = self.hdd.write_dma_callback(fis)
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elif fis.command == regs["READ_DMA_EXT"]:
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resp = self.hdd.read_dma_callback(fis)
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elif isinstance(fis, FIS_DATA):
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resp = self.hdd.data_callback(fis)
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if resp is not None:
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for packet in resp:
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self.transport.send(packet)
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# HDD model
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def print_hdd(s):
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print_with_prefix(s, "[HDD]: ")
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class HDDMemRegion:
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def __init__(self, base, count, sector_size):
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self.base = base
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self.count = count
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self.data = [0]*(count*sector_size//4)
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class HDD(Module):
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def __init__(self,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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hdd_debug=False,
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):
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###
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self.submodules.phy = PHYLayer()
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self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
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self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)
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self.submodules.command = CommandLayer(self.transport)
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self.command.set_hdd(self)
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self.debug = hdd_debug
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self.mem = None
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self.wr_sector = 0
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self.wr_end_sector = 0
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self.rd_sector = 0
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self.rx_end_sector = 0
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def malloc(self, sector, count):
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if self.debug:
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s = "Allocating {n} sectors: {s} to {e}".format(n=count, s=sector, e=sector+count)
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s += " ({} KB)".format(count*logical_sector_size//1024)
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print_hdd(s)
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self.mem = HDDMemRegion(sector, count, logical_sector_size)
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def write(self, sector, data):
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n = math.ceil(dwords2sectors(len(data)))
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if self.debug:
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if n == 1:
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s = "{}".format(sector)
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else:
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s = "{s} to {e}".format(s=sector, e=sector+n-1)
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print_hdd("Writing sector " + s)
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for i in range(len(data)):
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offset = sectors2dwords(sector)
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self.mem.data[offset+i] = data[i]
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def read(self, sector, count):
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if self.debug:
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if count == 1:
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s = "{}".format(sector)
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else:
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s = "{s} to {e}".format(s=sector, e=sector+count-1)
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print_hdd("Reading sector " + s)
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data = []
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for i in range(sectors2dwords(count)):
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data.append(self.mem.data[sectors2dwords(sector)+i])
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return data
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def write_dma_callback(self, fis):
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self.wr_sector = fis.lba_lsb + (fis.lba_msb << 32)
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self.wr_end_sector = self.wr_sector + fis.count
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return [FIS_DMA_ACTIVATE_D2H()]
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def read_dma_callback(self, fis):
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self.rd_sector = fis.lba_lsb + (fis.lba_msb << 32)
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self.rd_end_sector = self.rd_sector + fis.count
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packets = []
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while self.rd_sector != self.rd_end_sector:
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count = min(self.rd_end_sector-self.rd_sector, (fis_max_dwords*4)//logical_sector_size)
|
|
packet = self.read(self.rd_sector, count)
|
|
packet.insert(0, 0)
|
|
packets.append(FIS_DATA(packet, direction="D2H"))
|
|
self.rd_sector += count
|
|
packets.append(FIS_REG_D2H())
|
|
return packets
|
|
|
|
def data_callback(self, fis):
|
|
self.write(self.wr_sector, fis.packet[1:])
|
|
self.wr_sector += dwords2sectors(len(fis.packet[1:]))
|
|
if self.wr_sector == self.wr_end_sector:
|
|
return [FIS_REG_D2H()]
|
|
else:
|
|
return [FIS_DMA_ACTIVATE_D2H()]
|