50 lines
1.3 KiB
Python
50 lines
1.3 KiB
Python
import subprocess
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.core.link.scrambler import *
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from misoclib.mem.litesata.test.common import *
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class TB(Module):
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def __init__(self, length):
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self.submodules.scrambler = InsertReset(Scrambler())
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self.length = length
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def get_c_values(self, length):
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stdin = "0x%08x" %length
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with subprocess.Popen("./scrambler", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
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process.stdin.write(stdin.encode("ASCII"))
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out, err = process.communicate()
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return [int(e, 16) for e in out.decode("ASCII").split("\n")[:-1]]
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def gen_simulation(self, selfp):
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# init CRC
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selfp.scrambler.ce = 1
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selfp.scrambler.reset = 1
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yield
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selfp.scrambler.reset = 0
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# log results
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yield
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sim_values = []
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for i in range(self.length):
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sim_values.append(selfp.scrambler.value)
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yield
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# stop
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selfp.scrambler.ce = 0
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for i in range(32):
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yield
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# get C code reference
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c_values = self.get_c_values(self.length)
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# check results
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s, l, e = check(c_values, sim_values)
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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from migen.sim.generic import run_simulation
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length = 8192
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run_simulation(TB(length), ncycles=length+100, vcd_name="my.vcd")
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