Florent Kermarrec 31956de790 dvisampler/edid: fix sda sampling, needs to be similar to scl. ... Video sources with high scl frequency were not able to access EDID information through I2C. I2C start was not detected correctly and was randomly reseting the fsm during transfers.(seen with litescope)		2015-09-10 20:51:10 +02:00
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__init__.py	misoclib/video/dvisampler: add fifo_depth parameter	2015-07-13 11:03:33 +02:00
analysis.py	misoclib/video/dvisampler: add fifo_depth parameter	2015-07-13 11:03:33 +02:00
chansync.py	global: pep8 (E302)	2015-04-13 16:47:22 +02:00
charsync.py	global: pep8 (E302)	2015-04-13 16:47:22 +02:00
clocking.py	global: more pep8	2015-04-13 18:02:26 +02:00
common.py	video: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today's SoCs)	2015-03-01 10:07:52 +01:00
datacapture.py	global: more pep8	2015-04-13 18:02:26 +02:00
debug.py	global: pep8 (E302)	2015-04-13 16:47:22 +02:00
decoding.py	global: pep8 (E302)	2015-04-13 16:47:22 +02:00
dma.py	global: pep8 (E302)	2015-04-13 16:47:22 +02:00
edid.py	dvisampler/edid: fix sda sampling, needs to be similar to scl.	2015-09-10 20:51:10 +02:00
wer.py	global: pep8 (E302)	2015-04-13 16:47:22 +02:00