20 lines
372 B
Python
20 lines
372 B
Python
from migen.fhdl.std import *
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from migen.genlib.complex import *
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from migen.fhdl import verilog
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class Example(Module):
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def __init__(self):
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w = Complex(32, 42)
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A = SignalC(16)
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B = SignalC(16)
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Bw = SignalC(16, variable=True)
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C = SignalC(16)
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D = SignalC(16)
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self.sync += [
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Bw.eq(B*w),
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C.eq(A + Bw),
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D.eq(A - Bw)
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]
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print(verilog.convert(Example()))
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