152 lines
3.6 KiB
Python
152 lines
3.6 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.fsm import FSM, NextState
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class K7SATAPHYReconfig(Module):
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def __init__(self, channel_drp, mmcm_drp):
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self.speed = Signal(3)
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###
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speed_r = Signal(3)
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speed_change = Signal()
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self.sync += speed_r.eq(speed)
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self.comb += speed_change.eq(speed != speed_r)
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drp_sel = Signal()
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drp = DRPBus()
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self.comb += \
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If(sel,
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Record.connect(drp, mmcm_drp),
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).Else(
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Record.connect(drp, channel_drp)
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)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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# Todo
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fsm.act("IDLE",
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sel.eq(0),
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)
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class K7SATAPHYClocking(Module):
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def __init__(self, pads, gtx):
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self.reset = Signal()
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self.transceiver_reset = Signal()
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self.cd_sata_tx = ClockDomain()
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self.cd_sata_rx = ClockDomain()
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# TX clocking
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refclk = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_I=pads.refclk_p,
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i_IB=pads.refclk_n,
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o_O=refclk
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)
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mmcm_reset = Signal()
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mmcm_locked = Signal()
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mmcm_drp = DRP()
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mmcm_fb = Signal()
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mmcm_clk_i = Signal()
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mmcm_clk_o = Signal()
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self.specials += [
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Instance("BUFG", i_I=refclk, o_O=mmcm_clk_i),
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Instance("MMCME2_ADV",
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p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked,
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# DRP
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i_DCLK=mmcm_drp.clk, i_DEN=mmcm_drp.den, o_DRDY=mmcm_drp.rdy, i_DWE=mmcm_drp.we,
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i_DADDR=mmcm_drp.addr, i_DI=mmcm_drp.di, i_DO=mmcm_drp.do,
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT_F=8.000, CLKFBOUT_PHASE=0.000, p_DIVCLK_DIVIDE=2,
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i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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# CLK0
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p_CLKOUT0_DIVIDE_F=4.000, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk_o,
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),
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Instance("BUFG", i_I=mmcm_clk_o, o_O=self.cd_sata_tx.clk),
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]
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# RX clocking
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self.specials += [
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Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
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]
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self.comb += [
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gtx.rxusrclk.eq(self.cd_sata_rx.clk),
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gtx.rxusrclk2.eq(self.cd_sata_rx.clk)
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]
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# TX buffer bypass logic
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self.comb += [
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self.txphdlyreset.eq(0),
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self.txphalignen.eq(0),
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self.txdlyen.eq(0),
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self.txphalign.eq(0),
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self.txphinit.eq(0)
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]
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# once channel TX is reseted, reset TX buffer
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txbuffer_reseted = Signal()
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self.sync += \
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If(gtx.txresetdone,
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If(~txbuffer_reseted,
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gtx.txdlyreset.eq(1),
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txbuffer_reseted.eq(1)
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).Else(
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gtx.txdlyreset.eq(0)
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)
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)
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# RX buffer bypass logic
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self.comb += [
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gtx.rxphdlyreset.eq(0),
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gtx.rxdlyen.eq(0),
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gtx.rxphalign.eq(0),
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gtx.rxphalignen.eq(0),
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]
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# wait till CDR is locked
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cdr_cnt = Signal(14, reset=0b10011100010000)
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cdr_locked = Signal()
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self.sync += \
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If(cdr_cnt != 0,
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cdr_cnt.eq(cdr_cnt - 1)
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).Else(
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cdr_locked.eq(1)
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)
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# once CDR is locked and channel RX reseted, reset RX buffer
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rxbuffer_reseted = Signal()
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self.sync += \
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If(cdr_locked & gtx.rxresetdone,
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If(~rxbuffer_reseted,
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gtx.rxdlyreset.eq(1),
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rxbuffer_reseted.eq(1)
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).Else(
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gtx.rxdlyreset.eq(0)
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)
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)
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# Reset
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self.comb += [
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# GTXE2
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gtx.rxuserrdy.eq(gtx.cplllock),
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gtx.txuserrdy.eq(gtx.cplllock),
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# TX
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gtx.gttxreset.eq(self.reset | self.transceiver_reset | ~gtx.cplllock),
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# RX
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gtx.gtrxreset.eq(self.reset | self.transceiver_reset | ~gtx.cplllock),
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# PLL
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gtx.pllreset.eq(self.reset)
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]
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# SATA TX/RX clock domains
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self.specials += [
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AsyncResetSynchronizer(self.cd_sata_tx, ~mmcm_locked | ~gtx.txresetdone),
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AsyncResetSynchronizer(self.cd_sata_rx, ~gtx.cplllock | ~gtx.rxphaligndone),
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]
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# Dynamic Reconfiguration
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self.submodules.reconfig = K7SATAPHYReconfig(mmcm_drp, gtx.drp)
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