21 lines
564 B
Python
21 lines
564 B
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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class CRG(Module):
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def get_clock_domains(self):
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r = dict()
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for k, v in self.__dict__.items():
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if isinstance(v, ClockDomain):
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r[v.name] = v
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return r
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class SimpleCRG(CRG):
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def __init__(self, platform, clk_name, rst_name, rst_invert=False):
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self.cd = ClockDomain("sys")
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platform.request(clk_name, None, self.cd.clk)
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if rst_invert:
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rst_n = platform.request(rst_name)
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self.comb += self.cd.rst.eq(~rst_n)
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else:
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platform.request(rst_name, None, self.cd.rst)
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